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23#include <common.h>
24#include <command.h>
25#include <pci.h>
26#include <asm/processor.h>
27#include <asm/mmu.h>
28#include <asm/immap_85xx.h>
29#include <asm/fsl_pci.h>
30#include <asm/fsl_ddr_sdram.h>
31#include <asm/fsl_serdes.h>
32#include <asm/io.h>
33#include <miiphy.h>
34#include <libfdt.h>
35#include <fdt_support.h>
36#include <fsl_mdio.h>
37#include <tsec.h>
38#include <netdev.h>
39
40#include "../common/sgmii_riser.h"
41
42int checkboard (void)
43{
44 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
45 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
46 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
47 u8 vboot;
48 u8 *pixis_base = (u8 *)PIXIS_BASE;
49
50 if ((uint)&gur->porpllsr != 0xe00e0000) {
51 printf("immap size error %lx\n",(ulong)&gur->porpllsr);
52 }
53 printf ("Board: MPC8544DS, Sys ID: 0x%02x, "
54 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
55 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
56 in_8(pixis_base + PIXIS_PVER));
57
58 vboot = in_8(pixis_base + PIXIS_VBOOT);
59 if (vboot & PIXIS_VBOOT_FMAP)
60 printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
61 else
62 puts ("Promjet\n");
63
64 lbc->ltesr = 0xffffffff;
65 lbc->lteir = 0xffffffff;
66 ecm->eedr = 0xffffffff;
67 ecm->eeer = 0xffffffff;
68
69 return 0;
70}
71
72#ifdef CONFIG_PCI1
73static struct pci_controller pci1_hose;
74#endif
75
76#ifdef CONFIG_PCIE3
77static struct pci_controller pcie3_hose;
78#endif
79
80void pci_init_board(void)
81{
82 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
83 struct fsl_pci_info pci_info;
84 u32 devdisr, pordevsr, io_sel;
85 u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
86 int first_free_busno = 0;
87
88 int pcie_ep, pcie_configured;
89
90 devdisr = in_be32(&gur->devdisr);
91 pordevsr = in_be32(&gur->pordevsr);
92 porpllsr = in_be32(&gur->porpllsr);
93 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
94
95 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
96
97 puts("\n");
98
99#ifdef CONFIG_PCIE3
100 pcie_configured = is_serdes_configured(PCIE3);
101
102 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
103
104 set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_4M,
105 LAW_TRGT_IF_PCIE_3);
106 SET_STD_PCIE_INFO(pci_info, 3);
107 pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info.regs);
108
109
110 pci_set_region(&pcie3_hose.regions[0],
111 CONFIG_SYS_PCIE3_MEM_BUS2,
112 CONFIG_SYS_PCIE3_MEM_PHYS2,
113 CONFIG_SYS_PCIE3_MEM_SIZE2,
114 PCI_REGION_MEM);
115
116 pcie3_hose.region_count = 1;
117
118 printf("PCIE3: connected to ULI as %s (base addr %lx)\n",
119 pcie_ep ? "Endpoint" : "Root Complex",
120 pci_info.regs);
121 first_free_busno = fsl_pci_init_port(&pci_info,
122 &pcie3_hose, first_free_busno);
123
124
125
126
127
128 in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS);
129 } else {
130 printf("PCIE3: disabled\n");
131 }
132 puts("\n");
133#else
134 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3);
135#endif
136
137#ifdef CONFIG_PCIE1
138 SET_STD_PCIE_INFO(pci_info, 1);
139 first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE1, &pci_info);
140#else
141 setbits_be32(&gur->devdisr, _DEVDISR_PCIE1);
142#endif
143
144#ifdef CONFIG_PCIE2
145 SET_STD_PCIE_INFO(pci_info, 2);
146 first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE2, &pci_info);
147#else
148 setbits_be32(&gur->devdisr, _DEVDISR_PCIE2);
149#endif
150
151#ifdef CONFIG_PCI1
152 pci_speed = 66666000;
153 pci_32 = 1;
154 pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
155 pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
156
157 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
158 SET_STD_PCI_INFO(pci_info, 1);
159 set_next_law(pci_info.mem_phys,
160 law_size_bits(pci_info.mem_size), pci_info.law);
161 set_next_law(pci_info.io_phys,
162 law_size_bits(pci_info.io_size), pci_info.law);
163
164 pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
165 printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
166 (pci_32) ? 32 : 64,
167 (pci_speed == 33333000) ? "33" :
168 (pci_speed == 66666000) ? "66" : "unknown",
169 pci_clk_sel ? "sync" : "async",
170 pci_agent ? "agent" : "host",
171 pci_arb ? "arbiter" : "external-arbiter",
172 pci_info.regs);
173
174 first_free_busno = fsl_pci_init_port(&pci_info,
175 &pci1_hose, first_free_busno);
176 } else {
177 printf("PCI: disabled\n");
178 }
179
180 puts("\n");
181#else
182 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1);
183#endif
184}
185
186int last_stage_init(void)
187{
188 return 0;
189}
190
191
192unsigned long
193get_board_sys_clk(ulong dummy)
194{
195 u8 i, go_bit, rd_clks;
196 ulong val = 0;
197 u8 *pixis_base = (u8 *)PIXIS_BASE;
198
199 go_bit = in_8(pixis_base + PIXIS_VCTL);
200 go_bit &= 0x01;
201
202 rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
203 rd_clks &= 0x1C;
204
205
206
207
208
209
210
211 if (go_bit) {
212 if (rd_clks == 0x1c)
213 i = in_8(pixis_base + PIXIS_AUX);
214 else
215 i = in_8(pixis_base + PIXIS_SPD);
216 } else {
217 i = in_8(pixis_base + PIXIS_SPD);
218 }
219
220 i &= 0x07;
221
222 switch (i) {
223 case 0:
224 val = 33333333;
225 break;
226 case 1:
227 val = 40000000;
228 break;
229 case 2:
230 val = 50000000;
231 break;
232 case 3:
233 val = 66666666;
234 break;
235 case 4:
236 val = 83000000;
237 break;
238 case 5:
239 val = 100000000;
240 break;
241 case 6:
242 val = 133333333;
243 break;
244 case 7:
245 val = 166666666;
246 break;
247 }
248
249 return val;
250}
251
252
253#define MIIM_CIS8204_SLED_CON 0x1b
254#define MIIM_CIS8204_SLEDCON_INIT 0x1115
255
256
257
258int board_phy_config(struct phy_device *phydev)
259{
260 static int do_once;
261 uint phyid;
262 struct mii_dev *bus = phydev->bus;
263
264 if (phydev->drv->config)
265 phydev->drv->config(phydev);
266 if (do_once)
267 return 0;
268
269 for (phyid = 0; phyid < 4; phyid++)
270 bus->write(bus, phyid, MDIO_DEVAD_NONE, MIIM_CIS8204_SLED_CON,
271 MIIM_CIS8204_SLEDCON_INIT);
272
273 do_once = 1;
274
275 return 0;
276}
277
278
279int board_eth_init(bd_t *bis)
280{
281#ifdef CONFIG_TSEC_ENET
282 struct fsl_pq_mdio_info mdio_info;
283 struct tsec_info_struct tsec_info[2];
284 int num = 0;
285
286#ifdef CONFIG_TSEC1
287 SET_STD_TSEC_INFO(tsec_info[num], 1);
288 if (is_serdes_configured(SGMII_TSEC1)) {
289 puts("eTSEC1 is in sgmii mode.\n");
290 tsec_info[num].flags |= TSEC_SGMII;
291 }
292 num++;
293#endif
294#ifdef CONFIG_TSEC3
295 SET_STD_TSEC_INFO(tsec_info[num], 3);
296 if (is_serdes_configured(SGMII_TSEC3)) {
297 puts("eTSEC3 is in sgmii mode.\n");
298 tsec_info[num].flags |= TSEC_SGMII;
299 }
300 num++;
301#endif
302
303 if (!num) {
304 printf("No TSECs initialized\n");
305
306 return 0;
307 }
308
309 if (is_serdes_configured(SGMII_TSEC1) ||
310 is_serdes_configured(SGMII_TSEC3)) {
311 fsl_sgmii_riser_init(tsec_info, num);
312 }
313
314 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
315 mdio_info.name = DEFAULT_MII_NAME;
316 fsl_pq_mdio_init(bis, &mdio_info);
317
318 tsec_eth_init(bis, tsec_info, num);
319#endif
320 return pci_eth_init(bis);
321}
322
323#if defined(CONFIG_OF_BOARD_SETUP)
324void ft_board_setup(void *blob, bd_t *bd)
325{
326 ft_cpu_setup(blob, bd);
327
328 FT_FSL_PCI_SETUP;
329
330#ifdef CONFIG_FSL_SGMII_RISER
331 fsl_sgmii_riser_fdt_fixup(blob);
332#endif
333}
334#endif
335
