LXR uboot/board/rsdproto/rsdproto.c

   1/*
   2 * (C) Copyright 2000
   3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   4 * Marius Groeger <mgroeger@sysgo.de>
   5 *
   6 * See file CREDITS for list of people who contributed to this
   7 * project.
   8 *
   9 * This program is free software; you can redistribute it and/or
  10 * modify it under the terms of the GNU General Public License as
  11 * published by the Free Software Foundation; either version 2 of
  12 * the License, or (at your option) any later version.
  13 *
  14 * This program is distributed in the hope that it will be useful,
  15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 * GNU General Public License for more details.
  18 *
  19 * You should have received a copy of the GNU General Public License
  20 * along with this program; if not, write to the Free Software
  21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22 * MA 02111-1307 USA
  23 */
  24
  25#include <common.h>
  26#include <ioports.h>
  27#include <mpc8260.h>
  28#include <i2c.h>
  29#include <bcd.h>
  30
  31/* define to initialise the SDRAM on the local bus */
  32#undef INIT_LOCAL_BUS_SDRAM
  33
  34/* I2C Bus adresses for PPC & Protocol board */
  35#define PPC8260_I2C_ADR         0x30    /*(0)011.0000 */
  36#define LM84_PPC_I2C_ADR        0x2A    /*(0)010.1010 */
  37#define LM84_SHARC_I2C_ADR      0x29    /*(0)010.1001 */
  38#define VIRTEX_I2C_ADR          0x25    /*(0)010.0101 */
  39#define X24645_PPC_I2C_ADR      0x00    /*(0)00X.XXXX  -> be careful ! No other i2c-chip should have an adress beginning with (0)00 !!! */
  40#define RS5C372_PPC_I2C_ADR     0x32    /*(0)011.0010  -> this adress is programmed by the manufacturer and cannot be changed !!! */
  41
  42/*
  43 * I/O Port configuration table
  44 *
  45 * if conf is 1, then that port pin will be configured at boot time
  46 * according to the five values podr/pdir/ppar/psor/pdat for that entry
  47 */
  48
  49const iop_conf_t iop_conf_tab[4][32] = {
  50
  51    /* Port A configuration */
  52    {   /*            conf ppar psor pdir podr pdat */
  53        /* PA31 */ {   0,   0,   0,   0,   0,   0   },
  54        /* PA30 */ {   0,   0,   0,   0,   0,   0   },
  55        /* PA29 */ {   0,   0,   0,   0,   0,   0   },
  56        /* PA28 */ {   0,   0,   0,   0,   0,   0   },
  57        /* PA27 */ {   0,   0,   0,   0,   0,   0   },
  58        /* PA26 */ {   0,   0,   0,   0,   0,   0   },
  59        /* PA25 */ {   0,   0,   0,   0,   0,   0   },
  60        /* PA24 */ {   0,   0,   0,   0,   0,   0   },
  61        /* PA23 */ {   0,   0,   0,   0,   0,   0   },
  62        /* PA22 */ {   0,   0,   0,   0,   0,   0   },
  63        /* PA21 */ {   0,   0,   0,   0,   0,   0   },
  64        /* PA20 */ {   0,   0,   0,   0,   0,   0   },
  65        /* PA19 */ {   0,   0,   0,   0,   0,   0   },
  66        /* PA18 */ {   0,   0,   0,   0,   0,   0   },
  67        /* PA17 */ {   0,   0,   0,   0,   0,   0   },
  68        /* PA16 */ {   0,   0,   0,   0,   0,   0   },
  69        /* PA15 */ {   0,   0,   0,   0,   0,   0   },
  70        /* PA14 */ {   0,   0,   0,   0,   0,   0   },
  71        /* PA13 */ {   0,   0,   0,   0,   0,   0   },
  72        /* PA12 */ {   0,   0,   0,   0,   0,   0   },
  73        /* PA11 */ {   0,   0,   0,   0,   0,   0   },
  74        /* PA10 */ {   0,   0,   0,   0,   0,   0   },
  75        /* PA9  */ {   0,   0,   0,   0,   0,   0   },
  76        /* PA8  */ {   0,   0,   0,   0,   0,   0   },
  77        /* PA7  */ {   0,   0,   0,   0,   0,   0   },
  78        /* PA6  */ {   0,   0,   0,   0,   0,   0   },
  79        /* PA5  */ {   0,   0,   0,   0,   0,   0   },
  80        /* PA4  */ {   0,   0,   0,   0,   0,   0   },
  81        /* PA3  */ {   0,   0,   0,   0,   0,   0   },
  82        /* PA2  */ {   0,   0,   0,   0,   0,   0   },
  83        /* PA1  */ {   0,   0,   0,   0,   0,   0   },
  84        /* PA0  */ {   0,   0,   0,   0,   0,   0   }
  85    },
  86
  87
  88    {   /*            conf ppar psor pdir podr pdat */
  89        /* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
  90        /* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
  91        /* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
  92        /* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
  93        /* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
  94        /* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
  95        /* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
  96        /* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
  97        /* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
  98        /* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
  99        /* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
 100        /* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
 101        /* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
 102        /* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
 103        /* PB17 */ {   0,   0,   0,   0,   0,   0   },
 104        /* PB16 */ {   0,   0,   0,   0,   0,   0   },
 105        /* PB15 */ {   0,   0,   0,   0,   0,   0   },
 106        /* PB14 */ {   0,   0,   0,   0,   0,   0   },
 107        /* PB13 */ {   0,   0,   0,   0,   0,   0   },
 108        /* PB12 */ {   0,   0,   0,   0,   0,   0   },
 109        /* PB11 */ {   0,   0,   0,   0,   0,   0   },
 110        /* PB10 */ {   0,   0,   0,   0,   0,   0   },
 111        /* PB9  */ {   0,   0,   0,   0,   0,   0   },
 112        /* PB8  */ {   0,   0,   0,   0,   0,   0   },
 113        /* PB7  */ {   0,   0,   0,   0,   0,   0   },
 114        /* PB6  */ {   0,   0,   0,   0,   0,   0   },
 115        /* PB5  */ {   0,   0,   0,   0,   0,   0   },
 116        /* PB4  */ {   0,   0,   0,   0,   0,   0   },
 117        /* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 118        /* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 119        /* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 120        /* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
 121    },
 122
 123
 124    {   /*            conf ppar psor pdir podr pdat */
 125        /* PC31 */ {   0,   0,   0,   0,   0,   0   },
 126        /* PC30 */ {   0,   0,   0,   0,   0,   0   },
 127        /* PC29 */ {   0,   0,   0,   0,   0,   0   },
 128        /* PC28 */ {   0,   0,   0,   0,   0,   0   },
 129        /* PC27 */ {   0,   0,   0,   0,   0,   0   },
 130        /* PC26 */ {   0,   0,   0,   0,   0,   0   },
 131        /* PC25 */ {   0,   0,   0,   0,   0,   0   },
 132        /* PC24 */ {   0,   0,   0,   0,   0,   0   },
 133        /* PC23 */ {   0,   0,   0,   0,   0,   0   },
 134        /* PC22 */ {   0,   0,   0,   0,   0,   0   },
 135        /* PC21 */ {   0,   0,   0,   0,   0,   0   },
 136        /* PC20 */ {   0,   0,   0,   0,   0,   0   },
 137        /* PC19 */ {   1,   1,   0,   0,   0,   0   },
 138        /* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* ETHRXCLK: CLK14 */
 139        /* PC17 */ {   0,   0,   0,   0,   0,   0   }, /* ETHTXCLK: CLK15 */
 140        /* PC16 */ {   0,   0,   0,   0,   0,   0   },
 141        /* PC15 */ {   0,   0,   0,   0,   0,   0   },
 142        /* PC14 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 UART CD/ */
 143        /* PC13 */ {   0,   0,   0,   0,   0,   0   },
 144        /* PC12 */ {   0,   0,   0,   0,   0,   0   },
 145        /* PC11 */ {   0,   0,   0,   0,   0,   0   },
 146        /* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* ETHMDC: GP */
 147        /* PC9  */ {   1,   0,   0,   1,   0,   0   }, /* ETHMDIO: GP */
 148        /* PC8  */ {   0,   0,   0,   0,   0,   0   },
 149        /* PC7  */ {   0,   0,   0,   0,   0,   0   },
 150        /* PC6  */ {   0,   0,   0,   0,   0,   0   },
 151        /* PC5  */ {   0,   0,   0,   0,   0,   0   },
 152        /* PC4  */ {   0,   0,   0,   0,   0,   0   },
 153        /* PC3  */ {   0,   0,   0,   0,   0,   0   },
 154        /* PC2  */ {   0,   0,   0,   0,   0,   0   },
 155        /* PC1  */ {   0,   0,   0,   0,   0,   0   },
 156        /* PC0  */ {   0,   0,   0,   0,   0,   0   }
 157    },
 158
 159
 160    {   /*            conf ppar psor pdir podr pdat */
 161        /* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 UART RxD */
 162        /* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 UART TxD */
 163        /* PD29 */ {   0,   0,   0,   0,   0,   0   },
 164        /* PD28 */ {   0,   0,   0,   0,   0,   0   },
 165        /* PD27 */ {   0,   0,   0,   0,   0,   0   },
 166        /* PD26 */ {   0,   0,   0,   0,   0,   0   },
 167        /* PD25 */ {   0,   0,   0,   0,   0,   0   },
 168        /* PD24 */ {   0,   0,   0,   0,   0,   0   },
 169        /* PD23 */ {   0,   0,   0,   0,   0,   0   },
 170        /* PD22 */ {   0,   0,   0,   0,   0,   0   },
 171        /* PD21 */ {   0,   0,   0,   0,   0,   0   },
 172        /* PD20 */ {   0,   0,   0,   0,   0,   0   },
 173        /* PD19 */ {   0,   0,   0,   0,   0,   0   },
 174        /* PD18 */ {   0,   0,   0,   0,   0,   0   },
 175        /* PD17 */ {   0,   0,   0,   0,   0,   0   },
 176        /* PD16 */ {   0,   0,   0,   0,   0,   0   },
 177        /* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
 178        /* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
 179        /* PD13 */ {   0,   0,   0,   0,   0,   0   },
 180        /* PD12 */ {   0,   0,   0,   0,   0,   0   },
 181        /* PD11 */ {   0,   0,   0,   0,   0,   0   },
 182        /* PD10 */ {   0,   0,   0,   0,   0,   0   },
 183        /* PD9  */ {   0,   0,   0,   0,   0,   0   },
 184        /* PD8  */ {   0,   0,   0,   0,   0,   0   },
 185        /* PD7  */ {   0,   0,   0,   0,   0,   0   },
 186        /* PD6  */ {   0,   0,   0,   0,   0,   0   },
 187        /* PD5  */ {   0,   0,   0,   0,   0,   0   },
 188        /* PD4  */ {   0,   0,   0,   0,   0,   0   },
 189        /* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 190        /* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 191        /* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 192        /* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
 193    }
 194};
 195
 196/* ------------------------------------------------------------------------- */
 197
 198struct tm {
 199        unsigned int tm_sec;
 200        unsigned int tm_min;
 201        unsigned int tm_hour;
 202        unsigned int tm_wday;
 203        unsigned int tm_mday;
 204        unsigned int tm_mon;
 205        unsigned int tm_year;
 206};
 207
 208void read_RS5C372_time (struct tm *timedate)
 209{
 210        unsigned char buffer[8];
 211
 212        if (! i2c_read (RS5C372_PPC_I2C_ADR, 0, 1, buffer, sizeof (buffer))) {
 213                timedate->tm_sec = bcd2bin (buffer[0]);
 214                timedate->tm_min = bcd2bin (buffer[1]);
 215                timedate->tm_hour = bcd2bin (buffer[2]);
 216                timedate->tm_wday = bcd2bin (buffer[3]);
 217                timedate->tm_mday = bcd2bin (buffer[4]);
 218                timedate->tm_mon = bcd2bin (buffer[5]);
 219                timedate->tm_year = bcd2bin (buffer[6]) + 2000;
 220        } else {
 221                /*printf("i2c error %02x\n", rc); */
 222                memset (timedate, 0, sizeof (struct tm));
 223        }
 224}
 225
 226/* ------------------------------------------------------------------------- */
 227
 228int read_LM84_temp (int address)
 229{
 230        unsigned char buffer[8];
 231        /*int rc;*/
 232
 233        if (! i2c_read (address, 0, 1, buffer, 1)) {
 234                return (int) buffer[0];
 235        } else {
 236                /*printf("i2c error %02x\n", rc); */
 237                return -42;
 238        }
 239}
 240
 241/* ------------------------------------------------------------------------- */
 242
 243/*
 244 * Check Board Identity:
 245 */
 246
 247int checkboard (void)
 248{
 249        struct tm timedate;
 250        unsigned int ppctemp, prottemp;
 251
 252        puts ("Board: Rohde & Schwarz 8260 Protocol Board\n");
 253
 254        /* initialise i2c */
 255        i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 256
 257        read_RS5C372_time (&timedate);
 258        printf ("  Time:  %02d:%02d:%02d\n",
 259                        timedate.tm_hour, timedate.tm_min, timedate.tm_sec);
 260        printf ("  Date:  %02d-%02d-%04d\n",
 261                        timedate.tm_mday, timedate.tm_mon, timedate.tm_year);
 262        ppctemp = read_LM84_temp (LM84_PPC_I2C_ADR);
 263        prottemp = read_LM84_temp (LM84_SHARC_I2C_ADR);
 264        printf ("  Temp:  PPC %d C, Protocol Board %d C\n",
 265                        ppctemp, prottemp);
 266
 267        return 0;
 268}
 269
 270/* ------------------------------------------------------------------------- */
 271
 272/*
 273 * Miscelaneous platform dependent initialisations while still
 274 * running in flash
 275 */
 276
 277int misc_init_f (void)
 278{
 279        return 0;
 280}
 281
 282/* ------------------------------------------------------------------------- */
 283
 284phys_size_t initdram (int board_type)
 285{
 286        volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 287        volatile memctl8260_t *memctl = &immap->im_memctl;
 288
 289#ifdef INIT_LOCAL_BUS_SDRAM
 290        volatile uchar *ramaddr8;
 291#endif
 292        volatile ulong *ramaddr32;
 293        ulong sdmr;
 294        int i;
 295
 296        /*
 297         * Only initialize SDRAM when running from FLASH.
 298         * When running from RAM, don't touch it.
 299         */
 300        if ((ulong) initdram & 0xff000000) {
 301                immap->im_siu_conf.sc_ppc_acr = 0x02;
 302                immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
 303                immap->im_siu_conf.sc_ppc_alrl = 0x89ABCDEF;
 304                immap->im_siu_conf.sc_lcl_acr = 0x02;
 305                immap->im_siu_conf.sc_lcl_alrh = 0x01234567;
 306                immap->im_siu_conf.sc_lcl_alrl = 0x89ABCDEF;
 307                /*
 308                 * Program local/60x bus Transfer Error Status and Control Regs:
 309                 * Disable parity errors
 310                 */
 311                immap->im_siu_conf.sc_tescr1 = 0x00040000;
 312                immap->im_siu_conf.sc_ltescr1 = 0x00040000;
 313
 314                /*
 315                 * Perform Power-Up Initialisation of SDRAM (see 8260 UM, 10.4.2)
 316                 *
 317                 * The appropriate BRx/ORx registers have already
 318                 * been set when we get here (see cpu_init_f). The
 319                 * SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
 320                 */
 321                memctl->memc_mptpr = 0x2000;
 322                memctl->memc_mar = 0x0200;
 323#ifdef INIT_LOCAL_BUS_SDRAM
 324                /* initialise local bus ram
 325                 *
 326                 * (using the PSRMR_ definitions is NOT an error here
 327                 * - the LSDMR has the same fields as the PSDMR!)
 328                 */
 329                memctl->memc_lsrt = 0x0b;
 330                memctl->memc_lurt = 0x00;
 331                ramaddr = (uchar *) PHYS_SDRAM_LOCAL;
 332                sdmr = CONFIG_SYS_LSDMR & ~(PSDMR_OP_MSK | PSDMR_RFEN | PSDMR_PBI);
 333                memctl->memc_lsdmr = sdmr | PSDMR_OP_PREA;
 334                *ramaddr = 0xff;
 335                for (i = 0; i < 8; i++) {
 336                        memctl->memc_lsdmr = sdmr | PSDMR_OP_CBRR;
 337                        *ramaddr = 0xff;
 338                }
 339                memctl->memc_lsdmr = sdmr | PSDMR_OP_MRW;
 340                *ramaddr = 0xff;
 341                memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_OP_NORM;
 342#endif
 343                /* initialise 60x bus ram */
 344                memctl->memc_psrt = 0x0b;
 345                memctl->memc_purt = 0x08;
 346                ramaddr32 = (ulong *) PHYS_SDRAM_60X;
 347                sdmr = CONFIG_SYS_PSDMR & ~(PSDMR_OP_MSK | PSDMR_RFEN | PSDMR_PBI);
 348                memctl->memc_psdmr = sdmr | PSDMR_OP_PREA;
 349                ramaddr32[0] = 0x00ff00ff;
 350                ramaddr32[1] = 0x00ff00ff;
 351                memctl->memc_psdmr = sdmr | PSDMR_OP_CBRR;
 352                for (i = 0; i < 8; i++) {
 353                        ramaddr32[0] = 0x00ff00ff;
 354                        ramaddr32[1] = 0x00ff00ff;
 355                }
 356                memctl->memc_psdmr = sdmr | PSDMR_OP_MRW;
 357                ramaddr32[0] = 0x00ff00ff;
 358                ramaddr32[1] = 0x00ff00ff;
 359                memctl->memc_psdmr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
 360        }
 361
 362        /* return the size of the 60x bus ram */
 363        return PHYS_SDRAM_60X_SIZE;
 364}
 365
 366/* ------------------------------------------------------------------------- */
 367
 368/*
 369 * Miscelaneous platform dependent initialisations after monitor
 370 * has been relocated into ram
 371 */
 372
 373int misc_init_r (void)
 374{
 375        printf ("misc_init_r\n");
 376        return (0);
 377}
 378