uboot/board/sbc8641d/sbc8641d.c
<<
>>
Prefs 
   1/*
   2 * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
   3 * Copyright 2007 Embedded Specialties, Inc.
   4 * Joe Hamman joe.hamman@embeddedspecialties.com
   5 *
   6 * Copyright 2004 Freescale Semiconductor.
   7 * Jeff Brown
   8 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
   9 *
  10 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
  11 *
  12 * See file CREDITS for list of people who contributed to this
  13 * project.
  14 *
  15 * This program is free software; you can redistribute it and/or
  16 * modify it under the terms of the GNU General Public License as
  17 * published by the Free Software Foundation; either version 2 of
  18 * the License, or (at your option) any later version.
  19 *
  20 * This program is distributed in the hope that it will be useful,
  21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23 * GNU General Public License for more details.
  24 *
  25 * You should have received a copy of the GNU General Public License
  26 * along with this program; if not, write to the Free Software
  27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28 * MA 02111-1307 USA
  29 */
  30
  31#include <common.h>
  32#include <command.h>
  33#include <pci.h>
  34#include <asm/processor.h>
  35#include <asm/immap_86xx.h>
  36#include <asm/fsl_pci.h>
  37#include <asm/fsl_ddr_sdram.h>
  38#include <asm/fsl_serdes.h>
  39#include <libfdt.h>
  40#include <fdt_support.h>
  41
  42long int fixed_sdram (void);
  43
  44int board_early_init_f (void)
  45{
  46        return 0;
  47}
  48
  49int checkboard (void)
  50{
  51        puts ("Board: Wind River SBC8641D\n");
  52
  53        return 0;
  54}
  55
  56phys_size_t initdram (int board_type)
  57{
  58        long dram_size = 0;
  59
  60#if defined(CONFIG_SPD_EEPROM)
  61        dram_size = fsl_ddr_sdram();
  62#else
  63        dram_size = fixed_sdram ();
  64#endif
  65
  66        debug ("    DDR: ");
  67        return dram_size;
  68}
  69
  70#if defined(CONFIG_SYS_DRAM_TEST)
  71int testdram (void)
  72{
  73        uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
  74        uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
  75        uint *p;
  76
  77        puts ("SDRAM test phase 1:\n");
  78        for (p = pstart; p < pend; p++)
  79                *p = 0xaaaaaaaa;
  80
  81        for (p = pstart; p < pend; p++) {
  82                if (*p != 0xaaaaaaaa) {
  83                        printf ("SDRAM test fails at: %08x\n", (uint) p);
  84                        return 1;
  85                }
  86        }
  87
  88        puts ("SDRAM test phase 2:\n");
  89        for (p = pstart; p < pend; p++)
  90                *p = 0x55555555;
  91
  92        for (p = pstart; p < pend; p++) {
  93                if (*p != 0x55555555) {
  94                        printf ("SDRAM test fails at: %08x\n", (uint) p);
  95                        return 1;
  96                }
  97        }
  98
  99        puts ("SDRAM test passed.\n");
 100        return 0;
 101}
 102#endif
 103
 104#if !defined(CONFIG_SPD_EEPROM)
 105/*
 106 * Fixed sdram init -- doesn't use serial presence detect.
 107 */
 108long int fixed_sdram (void)
 109{
 110#if !defined(CONFIG_SYS_RAMBOOT)
 111        volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 112        volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
 113
 114        ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
 115        ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
 116        ddr->cs2_bnds = CONFIG_SYS_DDR_CS2_BNDS;
 117        ddr->cs3_bnds = CONFIG_SYS_DDR_CS3_BNDS;
 118        ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
 119        ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
 120        ddr->cs2_config = CONFIG_SYS_DDR_CS2_CONFIG;
 121        ddr->cs3_config = CONFIG_SYS_DDR_CS3_CONFIG;
 122        ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
 123        ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
 124        ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
 125        ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
 126        ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1A;
 127        ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2;
 128        ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
 129        ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
 130        ddr->sdram_mode_cntl = CONFIG_SYS_DDR_MODE_CTL;
 131        ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 132        ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
 133        ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
 134
 135        asm ("sync;isync");
 136
 137        udelay (500);
 138
 139        ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1B;
 140        asm ("sync; isync");
 141
 142        udelay (500);
 143        ddr = &immap->im_ddr2;
 144
 145        ddr->cs0_bnds = CONFIG_SYS_DDR2_CS0_BNDS;
 146        ddr->cs1_bnds = CONFIG_SYS_DDR2_CS1_BNDS;
 147        ddr->cs2_bnds = CONFIG_SYS_DDR2_CS2_BNDS;
 148        ddr->cs3_bnds = CONFIG_SYS_DDR2_CS3_BNDS;
 149        ddr->cs0_config = CONFIG_SYS_DDR2_CS0_CONFIG;
 150        ddr->cs1_config = CONFIG_SYS_DDR2_CS1_CONFIG;
 151        ddr->cs2_config = CONFIG_SYS_DDR2_CS2_CONFIG;
 152        ddr->cs3_config = CONFIG_SYS_DDR2_CS3_CONFIG;
 153        ddr->timing_cfg_3 = CONFIG_SYS_DDR2_EXT_REFRESH;
 154        ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0;
 155        ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1;
 156        ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2;
 157        ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1A;
 158        ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2;
 159        ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1;
 160        ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2;
 161        ddr->sdram_mode_cntl = CONFIG_SYS_DDR2_MODE_CTL;
 162        ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL;
 163        ddr->sdram_data_init = CONFIG_SYS_DDR2_DATA_INIT;
 164        ddr->sdram_clk_cntl = CONFIG_SYS_DDR2_CLK_CTRL;
 165
 166        asm ("sync;isync");
 167
 168        udelay (500);
 169
 170        ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1B;
 171        asm ("sync; isync");
 172
 173        udelay (500);
 174#endif
 175        return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 176}
 177#endif                          /* !defined(CONFIG_SPD_EEPROM) */
 178
 179#if defined(CONFIG_PCI)
 180/*
 181 * Initialize PCI Devices, report devices found.
 182 */
 183
 184void pci_init_board(void)
 185{
 186        fsl_pcie_init_board(0);
 187}
 188#endif /* CONFIG_PCI */
 189
 190
 191#if defined(CONFIG_OF_BOARD_SETUP)
 192void ft_board_setup (void *blob, bd_t *bd)
 193{
 194        ft_cpu_setup(blob, bd);
 195
 196        FT_FSL_PCI_SETUP;
 197}
 198#endif
 199
 200void sbc8641d_reset_board (void)
 201{
 202        puts ("Resetting board....\n");
 203}
 204
 205/*
 206 * get_board_sys_clk
 207 *      Clock is fixed at 1GHz on this board. Used for CONFIG_SYS_CLK_FREQ
 208 */
 209
 210unsigned long get_board_sys_clk (ulong dummy)
 211{
 212        int i;
 213        ulong val = 0;
 214
 215        i = 5;
 216        i &= 0x07;
 217
 218        switch (i) {
 219        case 0:
 220                val = 33000000;
 221                break;
 222        case 1:
 223                val = 40000000;
 224                break;
 225        case 2:
 226                val = 50000000;
 227                break;
 228        case 3:
 229                val = 66000000;
 230                break;
 231        case 4:
 232                val = 83000000;
 233                break;
 234        case 5:
 235                val = 100000000;
 236                break;
 237        case 6:
 238                val = 134000000;
 239                break;
 240        case 7:
 241                val = 166000000;
 242                break;
 243        }
 244
 245        return val;
 246}
 247
 248void board_reset(void)
 249{
 250#ifdef CONFIG_SYS_RESET_ADDRESS
 251        ulong addr = CONFIG_SYS_RESET_ADDRESS;
 252
 253        /* flush and disable I/D cache */
 254        __asm__ __volatile__ ("mfspr    3, 1008"        ::: "r3");
 255        __asm__ __volatile__ ("ori      5, 5, 0xcc00"   ::: "r5");
 256        __asm__ __volatile__ ("ori      4, 3, 0xc00"    ::: "r4");
 257        __asm__ __volatile__ ("andc     5, 3, 5"        ::: "r5");
 258        __asm__ __volatile__ ("sync");
 259        __asm__ __volatile__ ("mtspr    1008, 4");
 260        __asm__ __volatile__ ("isync");
 261        __asm__ __volatile__ ("sync");
 262        __asm__ __volatile__ ("mtspr    1008, 5");
 263        __asm__ __volatile__ ("isync");
 264        __asm__ __volatile__ ("sync");
 265
 266        /*
 267         * SRR0 has system reset vector, SRR1 has default MSR value
 268         * rfi restores MSR from SRR1 and sets the PC to the SRR0 value
 269         */
 270        __asm__ __volatile__ ("mtspr    26, %0"         :: "r" (addr));
 271        __asm__ __volatile__ ("li       4, (1 << 6)"    ::: "r4");
 272        __asm__ __volatile__ ("mtspr    27, 4");
 273        __asm__ __volatile__ ("rfi");
 274#endif
 275}
 276
Hosted by Missing Link Electronics. The original LXR software by the LXR community, this experimental version by lxr@linux.no.