LXR uboot/board/ti/omap2420h4/omap2420h4.c

   1/*
   2 * (C) Copyright 2004
   3 * Texas Instruments, <www.ti.com>
   4 * Richard Woodruff <r-woodruff2@ti.com>
   5 *
   6 * See file CREDITS for list of people who contributed to this
   7 * project.
   8 *
   9 * This program is free software; you can redistribute it and/or
  10 * modify it under the terms of the GNU General Public License as
  11 * published by the Free Software Foundation; either version 2 of
  12 * the License, or (at your option) any later version.
  13 *
  14 * This program is distributed in the hope that it will be useful,
  15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 * GNU General Public License for more details.
  18 *
  19 * You should have received a copy of the GNU General Public License
  20 * along with this program; if not, write to the Free Software
  21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22 * MA 02111-1307 USA
  23 */
  24#include <common.h>
  25#include <netdev.h>
  26#include <asm/arch/omap2420.h>
  27#include <asm/io.h>
  28#include <asm/arch/bits.h>
  29#include <asm/arch/mux.h>
  30#include <asm/arch/sys_proto.h>
  31#include <asm/arch/sys_info.h>
  32#include <asm/arch/mem.h>
  33#include <i2c.h>
  34#include <asm/mach-types.h>
  35
  36DECLARE_GLOBAL_DATA_PTR;
  37
  38void wait_for_command_complete(unsigned int wd_base);
  39
  40/*******************************************************
  41 * Routine: delay
  42 * Description: spinning delay to use before udelay works
  43 ******************************************************/
  44static inline void delay (unsigned long loops)
  45{
  46        __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
  47                "bne 1b":"=r" (loops):"0" (loops));
  48}
  49
  50/*****************************************
  51 * Routine: board_init
  52 * Description: Early hardware init.
  53 *****************************************/
  54int board_init (void)
  55{
  56        gpmc_init(); /* in SRAM or SDRM, finish GPMC */
  57
  58        gd->bd->bi_arch_number = MACH_TYPE_OMAP_H4;             /* board id for linux */
  59        gd->bd->bi_boot_params = (OMAP2420_SDRC_CS0+0x100);     /* adress of boot parameters */
  60
  61        return 0;
  62}
  63
  64/**********************************************************
  65 * Routine: try_unlock_sram()
  66 * Description: If chip is GP type, unlock the SRAM for
  67 *  general use.
  68 ***********************************************************/
  69void try_unlock_sram(void)
  70{
  71        /* if GP device unlock device SRAM for general use */
  72        if (get_device_type() == GP_DEVICE) {
  73                __raw_writel(0xFF, A_REQINFOPERM0);
  74                __raw_writel(0xCFDE, A_READPERM0);
  75                __raw_writel(0xCFDE, A_WRITEPERM0);
  76        }
  77}
  78
  79/**********************************************************
  80 * Routine: s_init
  81 * Description: Does early system init of muxing and clocks.
  82 * - Called path is with sram stack.
  83 **********************************************************/
  84void s_init(void)
  85{
  86        int in_sdram = running_in_sdram();
  87
  88        watchdog_init();
  89        set_muxconf_regs();
  90        delay(100);
  91        try_unlock_sram();
  92
  93        if(!in_sdram)
  94                prcm_init();
  95
  96        peripheral_enable();
  97        icache_enable();
  98        if (!in_sdram)
  99                sdrc_init();
 100}
 101
 102/*******************************************************
 103 * Routine: misc_init_r
 104 * Description: Init ethernet (done here so udelay works)
 105 ********************************************************/
 106int misc_init_r (void)
 107{
 108        ether_init(); /* better done here so timers are init'ed */
 109        return(0);
 110}
 111
 112/****************************************
 113 * Routine: watchdog_init
 114 * Description: Shut down watch dogs
 115 *****************************************/
 116void watchdog_init(void)
 117{
 118        /* There are 4 watch dogs.  1 secure, and 3 general purpose.
 119        * The ROM takes care of the secure one. Of the 3 GP ones,
 120        * 1 can reset us directly, the other 2 only generate MPU interrupts.
 121        */
 122        __raw_writel(WD_UNLOCK1 ,WD2_BASE+WSPR);
 123        wait_for_command_complete(WD2_BASE);
 124        __raw_writel(WD_UNLOCK2 ,WD2_BASE+WSPR);
 125
 126#if MPU_WD_CLOCKED /* value 0x10 stick on aptix, BIT4 polarity seems oppsite*/
 127        __raw_writel(WD_UNLOCK1 ,WD3_BASE+WSPR);
 128        wait_for_command_complete(WD3_BASE);
 129        __raw_writel(WD_UNLOCK2 ,WD3_BASE+WSPR);
 130
 131        __raw_writel(WD_UNLOCK1 ,WD4_BASE+WSPR);
 132        wait_for_command_complete(WD4_BASE);
 133        __raw_writel(WD_UNLOCK2 ,WD4_BASE+WSPR);
 134#endif
 135}
 136
 137/******************************************************
 138 * Routine: wait_for_command_complete
 139 * Description: Wait for posting to finish on watchdog
 140 ******************************************************/
 141void wait_for_command_complete(unsigned int wd_base)
 142{
 143        int pending = 1;
 144        do {
 145                pending = __raw_readl(wd_base+WWPS);
 146        } while (pending);
 147}
 148
 149/*******************************************************************
 150 * Routine:ether_init
 151 * Description: take the Ethernet controller out of reset and wait
 152 *                 for the EEPROM load to complete.
 153 ******************************************************************/
 154void ether_init (void)
 155{
 156#ifdef CONFIG_DRIVER_LAN91C96
 157        int cnt = 20;
 158
 159        __raw_writeb(0x3,OMAP2420_CTRL_BASE+0x10a); /*protect->gpio95 */
 160
 161        __raw_writew(0x0, LAN_RESET_REGISTER);
 162        do {
 163                __raw_writew(0x1, LAN_RESET_REGISTER);
 164                udelay (100);
 165                if (cnt == 0)
 166                        goto h4reset_err_out;
 167                --cnt;
 168        } while (__raw_readw(LAN_RESET_REGISTER) != 0x1);
 169
 170        cnt = 20;
 171
 172        do {
 173                __raw_writew(0x0, LAN_RESET_REGISTER);
 174                udelay (100);
 175                if (cnt == 0)
 176                        goto h4reset_err_out;
 177                --cnt;
 178        } while (__raw_readw(LAN_RESET_REGISTER) != 0x0000);
 179        udelay (1000);
 180
 181        *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
 182        udelay (1000);
 183
 184        h4reset_err_out:
 185        return;
 186#endif
 187}
 188
 189/**********************************************
 190 * Routine: dram_init
 191 * Description: sets uboots idea of sdram size
 192 **********************************************/
 193int dram_init (void)
 194{
 195        unsigned int size0=0,size1=0;
 196        u32 mtype, btype, rev;
 197        u8 chg_on = 0x5; /* enable charge of back up battery */
 198        u8 vmode_on = 0x8C;
 199        #define NOT_EARLY 0
 200
 201        i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); /* need this a bit early */
 202
 203        btype = get_board_type();
 204        mtype = get_mem_type();
 205        rev = get_cpu_rev();
 206
 207        display_board_info(btype);
 208        if (btype == BOARD_H4_MENELAUS){
 209                update_mux(btype,mtype); /* combo part on menelaus */
 210                i2c_write(I2C_MENELAUS, 0x20, 1, &chg_on, 1); /*fix POR reset bug */
 211                i2c_write(I2C_MENELAUS, 0x2, 1, &vmode_on, 1); /* VCORE change on VMODE */
 212        }
 213
 214        if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) {
 215                do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY); /* init other chip select */
 216        }
 217        size0 = get_sdr_cs_size(SDRC_CS0_OSET);
 218        size1 = get_sdr_cs_size(SDRC_CS1_OSET);
 219
 220        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 221        gd->bd->bi_dram[0].size = size0;
 222        if(rev == CPU_2420_2422_ES1) /* ES1's 128MB remap granularity isn't worth doing */
 223                gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 224        else /* ES2 and above can remap at 32MB granularity */
 225                gd->bd->bi_dram[1].start = PHYS_SDRAM_1+size0;
 226        gd->bd->bi_dram[1].size = size1;
 227
 228        return 0;
 229}
 230
 231/**********************************************************
 232 * Routine: set_muxconf_regs
 233 * Description: Setting up the configuration Mux registers
 234 *              specific to the hardware
 235 *********************************************************/
 236void set_muxconf_regs (void)
 237{
 238        muxSetupSDRC();
 239        muxSetupGPMC();
 240        muxSetupUsb0();
 241        muxSetupUart3();
 242        muxSetupI2C1();
 243        muxSetupUART1();
 244        muxSetupLCD();
 245        muxSetupCamera();
 246        muxSetupMMCSD();
 247        muxSetupTouchScreen();
 248        muxSetupHDQ();
 249}
 250
 251/*****************************************************************
 252 * Routine: peripheral_enable
 253 * Description: Enable the clks & power for perifs (GPT2, UART1,...)
 254 ******************************************************************/
 255void peripheral_enable(void)
 256{
 257        unsigned int v, if_clks=0, func_clks=0;
 258
 259        /* Enable GP2 timer.*/
 260        if_clks |= BIT4;
 261        func_clks |= BIT4;
 262        v = __raw_readl(CM_CLKSEL2_CORE) | 0x4; /* Sys_clk input OMAP2420_GPT2 */
 263        __raw_writel(v, CM_CLKSEL2_CORE);
 264        __raw_writel(0x1, CM_CLKSEL_WKUP);
 265
 266#ifdef CONFIG_SYS_NS16550
 267        /* Enable UART1 clock */
 268        func_clks |= BIT21;
 269        if_clks |= BIT21;
 270#endif
 271        v = __raw_readl(CM_ICLKEN1_CORE) | if_clks;     /* Interface clocks on */
 272        __raw_writel(v,CM_ICLKEN1_CORE );
 273        v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; /* Functional Clocks on */
 274        __raw_writel(v, CM_FCLKEN1_CORE);
 275        delay(1000);
 276
 277#ifndef KERNEL_UPDATED
 278        {
 279#define V1 0xffffffff
 280#define V2 0x00000007
 281
 282                __raw_writel(V1, CM_FCLKEN1_CORE);
 283                __raw_writel(V2, CM_FCLKEN2_CORE);
 284                __raw_writel(V1, CM_ICLKEN1_CORE);
 285                __raw_writel(V1, CM_ICLKEN2_CORE);
 286        }
 287#endif
 288}
 289
 290/****************************************
 291 * Routine: muxSetupUsb0   (ostboot)
 292 * Description: Setup usb muxing
 293 *****************************************/
 294void muxSetupUsb0(void)
 295{
 296        volatile uint8   *MuxConfigReg;
 297        volatile uint32  *otgCtrlReg;
 298
 299        MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_PUEN;
 300        *MuxConfigReg &= (uint8)(~0x1F);
 301
 302        MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VP;
 303        *MuxConfigReg &= (uint8)(~0x1F);
 304
 305        MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VM;
 306        *MuxConfigReg &= (uint8)(~0x1F);
 307
 308        MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_RCV;
 309        *MuxConfigReg &= (uint8)(~0x1F);
 310
 311        MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_TXEN;
 312        *MuxConfigReg &= (uint8)(~0x1F);
 313
 314        MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_SE0;
 315        *MuxConfigReg &= (uint8)(~0x1F);
 316
 317        MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_DAT;
 318        *MuxConfigReg &= (uint8)(~0x1F);
 319
 320        /* setup for USB VBus detection */
 321        otgCtrlReg = (volatile uint32 *)USB_OTG_CTRL;
 322        *otgCtrlReg |= 0x00040000; /* bit 18 */
 323}
 324
 325/****************************************
 326 * Routine: muxSetupUart3   (ostboot)
 327 * Description: Setup uart3 muxing
 328 *****************************************/
 329void muxSetupUart3(void)
 330{
 331        volatile uint8 *MuxConfigReg;
 332
 333        MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_UART3_TX_IRTX;
 334        *MuxConfigReg &= (uint8)(~0x1F);
 335
 336        MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_UART3_RX_IRRX;
 337        *MuxConfigReg &= (uint8)(~0x1F);
 338}
 339
 340/****************************************
 341 * Routine: muxSetupI2C1   (ostboot)
 342 * Description: Setup i2c muxing
 343 *****************************************/
 344void muxSetupI2C1(void)
 345{
 346        volatile unsigned char  *MuxConfigReg;
 347
 348        /* I2C1 Clock pin configuration, PIN = M19 */
 349        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_I2C1_SCL;
 350        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 351
 352        /* I2C1 Data pin configuration, PIN = L15 */
 353        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_I2C1_SDA;
 354        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 355
 356        /* Pull-up required on data line */
 357        /* external pull-up already present. */
 358        /* *MuxConfigReg |= 0x18 ;*/ /* Mode = 0, PullTypeSel=PU, PullUDEnable=Enabled */
 359}
 360
 361/****************************************
 362 * Routine: muxSetupUART1  (ostboot)
 363 * Description: Set up uart1 muxing
 364 *****************************************/
 365void muxSetupUART1(void)
 366{
 367        volatile unsigned char  *MuxConfigReg;
 368
 369        /* UART1_CTS pin configuration, PIN = D21 */
 370        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_CTS;
 371        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 372
 373        /* UART1_RTS pin configuration, PIN = H21 */
 374        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RTS;
 375        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 376
 377        /* UART1_TX pin configuration, PIN = L20 */
 378        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_TX;
 379        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 380
 381        /* UART1_RX pin configuration, PIN = T21 */
 382        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RX;
 383        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 384}
 385
 386/****************************************
 387 * Routine: muxSetupLCD   (ostboot)
 388 * Description: Setup lcd muxing
 389 *****************************************/
 390void muxSetupLCD(void)
 391{
 392        volatile unsigned char  *MuxConfigReg;
 393
 394        /* LCD_D0 pin configuration, PIN = Y7  */
 395        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D0;
 396        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 397
 398        /* LCD_D1 pin configuration, PIN = P10 */
 399        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D1;
 400        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 401
 402        /* LCD_D2 pin configuration, PIN = V8  */
 403        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D2;
 404        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 405
 406        /* LCD_D3 pin configuration, PIN = Y8  */
 407        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D3;
 408        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 409
 410        /* LCD_D4 pin configuration, PIN = W8  */
 411        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D4;
 412        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 413
 414        /* LCD_D5 pin configuration, PIN = R10 */
 415        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D5;
 416        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 417
 418        /* LCD_D6 pin configuration, PIN = Y9  */
 419        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D6;
 420        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 421
 422        /* LCD_D7 pin configuration, PIN = V9  */
 423        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D7;
 424        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 425
 426        /* LCD_D8 pin configuration, PIN = W9  */
 427        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D8;
 428        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 429
 430        /* LCD_D9 pin configuration, PIN = P11 */
 431        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D9;
 432        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 433
 434        /* LCD_D10 pin configuration, PIN = V10 */
 435        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D10;
 436        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 437
 438        /* LCD_D11 pin configuration, PIN = Y10 */
 439        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D11;
 440        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 441
 442        /* LCD_D12 pin configuration, PIN = W10 */
 443        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D12;
 444        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 445
 446        /* LCD_D13 pin configuration, PIN = R11 */
 447        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D13;
 448        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 449
 450        /* LCD_D14 pin configuration, PIN = V11 */
 451        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D14;
 452        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 453
 454        /* LCD_D15 pin configuration, PIN = W11 */
 455        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D15;
 456        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 457
 458        /* LCD_D16 pin configuration, PIN = P12 */
 459        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D16;
 460        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 461
 462        /* LCD_D17 pin configuration, PIN = R12 */
 463        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D17;
 464        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 465
 466        /* LCD_PCLK pin configuration,   PIN = W6   */
 467        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_PCLK;
 468        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 469
 470        /* LCD_VSYNC pin configuration,  PIN = V7  */
 471        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_VSYNC;
 472        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 473
 474        /* LCD_HSYNC pin configuration,  PIN = Y6  */
 475        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_HSYNC;
 476        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 477
 478        /* LCD_ACBIAS pin configuration, PIN = W7 */
 479        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_ACBIAS;
 480        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 481}
 482
 483/****************************************
 484 * Routine: muxSetupCamera  (ostboot)
 485 * Description: Setup camera muxing
 486 *****************************************/
 487void muxSetupCamera(void)
 488{
 489        volatile unsigned char  *MuxConfigReg;
 490
 491        /* CAMERA_RSTZ  pin configuration, PIN = Y16 */
 492        /* CAM_RST is connected through the I2C IO expander.*/
 493        /* MuxConfigReg = (volatile unsigned char *), CONTROL_PADCONF_SYS_NRESWARM*/
 494        /* *MuxConfigReg = 0x00 ; / * Mode = 0, PUPD=Disabled   */
 495
 496        /* CAMERA_XCLK  pin configuration, PIN = U3 */
 497        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_XCLK;
 498        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 499
 500        /* CAMERA_LCLK  pin configuration, PIN = V5 */
 501        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_LCLK;
 502        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 503
 504        /* CAMERA_VSYNC pin configuration, PIN = U2 */
 505        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_VS,
 506                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 507
 508        /* CAMERA_HSYNC pin configuration, PIN = T3 */
 509        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_HS,
 510                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 511
 512        /* CAMERA_DAT0 pin configuration, PIN = T4 */
 513        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D0,
 514                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 515
 516        /* CAMERA_DAT1 pin configuration, PIN = V2 */
 517        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D1,
 518                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 519
 520        /* CAMERA_DAT2 pin configuration, PIN = V3 */
 521        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D2,
 522                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 523
 524        /* CAMERA_DAT3 pin configuration, PIN = U4 */
 525        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D3,
 526                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 527
 528        /* CAMERA_DAT4 pin configuration, PIN = W2 */
 529        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D4,
 530                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 531
 532        /* CAMERA_DAT5 pin configuration, PIN = V4 */
 533        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D5,
 534                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 535
 536        /* CAMERA_DAT6 pin configuration, PIN = W3 */
 537        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D6,
 538                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 539
 540        /* CAMERA_DAT7 pin configuration, PIN = Y2 */
 541        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D7,
 542                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 543
 544        /* CAMERA_DAT8 pin configuration, PIN = Y4 */
 545        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D8,
 546                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 547
 548        /* CAMERA_DAT9 pin configuration, PIN = V6 */
 549        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D9,
 550                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 551}
 552
 553/****************************************
 554 * Routine: muxSetupMMCSD (ostboot)
 555 * Description: set up MMC muxing
 556 *****************************************/
 557void muxSetupMMCSD(void)
 558{
 559        volatile unsigned char  *MuxConfigReg;
 560
 561        /* SDMMC_CLKI pin configuration,  PIN = H15 */
 562        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKI,
 563                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 564
 565        /* SDMMC_CLKO pin configuration,  PIN = G19 */
 566        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKO,
 567                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 568
 569        /* SDMMC_CMD pin configuration,   PIN = H18 */
 570        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD,
 571                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 572        /* External pull-ups are present. */
 573        /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
 574
 575        /* SDMMC_DAT0 pin configuration,  PIN = F20 */
 576        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT0,
 577                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 578        /* External pull-ups are present. */
 579        /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
 580
 581        /* SDMMC_DAT1 pin configuration,  PIN = H14 */
 582        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT1,
 583                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 584        /* External pull-ups are present. */
 585        /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
 586
 587        /* SDMMC_DAT2 pin configuration,  PIN = E19 */
 588        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT2,
 589                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 590        /* External pull-ups are present. */
 591        /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
 592
 593        /* SDMMC_DAT3 pin configuration,  PIN = D19 */
 594        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT3,
 595                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 596        /* External pull-ups are present. */
 597        /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
 598
 599        /* SDMMC_DDIR0 pin configuration, PIN = F19 */
 600        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR0,
 601                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 602
 603        /* SDMMC_DDIR1 pin configuration, PIN = E20 */
 604        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR1,
 605                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 606
 607        /* SDMMC_DDIR2 pin configuration, PIN = F18 */
 608        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR2,
 609                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 610
 611        /* SDMMC_DDIR3 pin configuration, PIN = E18 */
 612        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR3,
 613                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 614
 615        /* SDMMC_CDIR pin configuration,  PIN = G18 */
 616        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD_DIR,
 617                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 618
 619        /* MMC_CD pin configuration,      PIN = B3  ---2420IP ONLY---*/
 620        /* MMC_CD for 2422IP=K1 */
 621        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SDRC_A14,
 622                                   *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
 623
 624        /* MMC_WP pin configuration,      PIN = B4  */
 625        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SDRC_A13,
 626                                   *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
 627}
 628
 629/******************************************
 630 * Routine: muxSetupTouchScreen (ostboot)
 631 * Description:  Set up touch screen muxing
 632 *******************************************/
 633void muxSetupTouchScreen(void)
 634{
 635        volatile unsigned char  *MuxConfigReg;
 636
 637        /* SPI1_CLK pin configuration,  PIN = U18 */
 638        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_CLK,
 639                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 640
 641        /* SPI1_MOSI pin configuration, PIN = V20 */
 642        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SIMO,
 643                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 644
 645        /* SPI1_MISO pin configuration, PIN = T18 */
 646        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SOMI,
 647                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 648
 649        /* SPI1_nCS0 pin configuration, PIN = U19 */
 650        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_NCS0,
 651                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 652
 653        /* PEN_IRQ pin configuration,   PIN = P20 */
 654        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MCBSP1_FSR,
 655                                   *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
 656}
 657
 658/****************************************
 659 * Routine: muxSetupHDQ (ostboot)
 660 * Description: setup 1wire mux
 661 *****************************************/
 662void muxSetupHDQ(void)
 663{
 664        volatile unsigned char  *MuxConfigReg;
 665
 666        /* HDQ_SIO pin configuration,  PIN = N18 */
 667        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_HDQ_SIO,
 668                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 669}
 670
 671/***************************************************************
 672 * Routine: muxSetupGPMC (ostboot)
 673 * Description: Configures balls which cam up in protected mode
 674 ***************************************************************/
 675void muxSetupGPMC(void)
 676{
 677        volatile uint8 *MuxConfigReg;
 678        volatile unsigned int *MCR = (volatile unsigned int *)0x4800008C;
 679
 680        /* gpmc_io_dir */
 681        *MCR = 0x19000000;
 682
 683        /* NOR FLASH CS0 */
 684        /* signal - Gpmc_clk; pin - J4; offset - 0x0088; mode - 0; Byte-3       Pull/up - N/A */
 685        MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_D2_BYTE3,
 686                                   *MuxConfigReg = 0x00 ;
 687
 688        /* signal - Gpmc_iodir; pin - n2; offset - 0x008C; mode - 1; Byte-3     Pull/up - N/A */
 689        MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE3,
 690                                   *MuxConfigReg = 0x01 ;
 691
 692        /* MPDB(Multi Port Debug Port) CS1 */
 693        /* signal - gpmc_ncs1; pin - N8; offset - 0x008C; mode - 0; Byte-1      Pull/up - N/A */
 694        MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE1,
 695                                   *MuxConfigReg = 0x00 ;
 696
 697        /* signal - Gpmc_ncs2; pin - E2; offset - 0x008C; mode - 0; Byte-2      Pull/up - N/A */
 698        MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE2,
 699                                   *MuxConfigReg = 0x00 ;
 700}
 701
 702/****************************************************************
 703 * Routine: muxSetupSDRC  (ostboot)
 704 * Description: Configures balls which come up in protected mode
 705 ****************************************************************/
 706void muxSetupSDRC(void)
 707{
 708        volatile uint8 *MuxConfigReg;
 709
 710        /* signal - sdrc_ncs1; pin - C12; offset - 0x00A0; mode - 0; Byte-1     Pull/up - N/A */
 711        MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_NCS0_BYTE1,
 712                                   *MuxConfigReg = 0x00 ;
 713
 714        /* signal - sdrc_a12; pin - D11; offset - 0x0030; mode - 0; Byte-2      Pull/up - N/A */
 715        MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_A14_BYTE2,
 716                                   *MuxConfigReg = 0x00 ;
 717
 718        /* signal - sdrc_cke1; pin - B13; offset - 0x00A0; mode - 0; Byte-3     Pull/up - N/A */
 719        MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_NCS0_BYTE3,
 720                                   *MuxConfigReg = 0x00;
 721
 722        if (get_cpu_type() == CPU_2422) {
 723                MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_A14_BYTE0,
 724                                           *MuxConfigReg = 0x1b;
 725        }
 726}
 727
 728/*****************************************************************************
 729 * Routine: update_mux()
 730 * Description: Update balls which are different beween boards.  All should be
 731 *              updated to match functionaly.  However, I'm only updating ones
 732 *              which I'll be using for now.  When power comes into play they
 733 *              all need updating.
 734 *****************************************************************************/
 735void update_mux(u32 btype,u32 mtype)
 736{
 737        u32 cpu, base = OMAP2420_CTRL_BASE;
 738        cpu = get_cpu_type();
 739
 740        if (btype == BOARD_H4_MENELAUS) {
 741                if (cpu == CPU_2420) {
 742                        /* PIN = B3,  GPIO.0->KBR5,      mode 3,  (pun?),-DO-*/
 743                        __raw_writeb(0x3, base+0x30);
 744                        /* PIN = B13, GPIO.38->KBC6,     mode 3,  (pun?)-DO-*/
 745                        __raw_writeb(0x3, base+0xa3);
 746                        /* PIN = F1, GPIO.25->HSUSBxx    mode 3,  (for external HS USB)*/
 747                        /* PIN = H1, GPIO.26->HSUSBxx    mode 3,  (for external HS USB)*/
 748                        /* PIN = K1, GPMC_ncs6           mode 0,  (on board nand access)*/
 749                        /* PIN = L2, GPMC_ncs67          mode 0,  (for external HS USB)*/
 750                        /* PIN = M1 (HSUSBOTG) */
 751                        /* PIN = P1, GPIO.35->MEN_POK    mode 3,  (menelaus powerok)-DO-*/
 752                        __raw_writeb(0x3, base+0x9d);
 753                        /* PIN = U32, (WLAN_CLKREQ) */
 754                        /* PIN = Y11, WLAN */
 755                        /* PIN = AA4, GPIO.15->KBC2,     mode 3,  -DO- */
 756                        __raw_writeb(0x3, base+0xe7);
 757                        /* PIN = AA8, mDOC */
 758                        /* PIN = AA10, BT */
 759                        /* PIN = AA13, WLAN */
 760                        /* PIN = M18 GPIO.96->MMC2_WP    mode 3   -DO- */
 761                        __raw_writeb(0x3, base+0x10e);
 762                        /* PIN = N19 GPIO.98->WLAN_INT   mode 3   -DO- */
 763                        __raw_writeb(0x3, base+0x110);
 764                        /* PIN = J15 HHUSB */
 765                        /* PIN = H19 HSUSB */
 766                        /* PIN = W13, P13, R13, W16 ... */
 767                        /* PIN = V12 GPIO.25->I2C_CAMEN  mode 3   -DO- */
 768                        __raw_writeb(0x3, base+0xde);
 769                        /* PIN = W19 sys_nirq->MENELAUS_INT mode 0 -DO- */
 770                        __raw_writeb(0x0, base+0x12c);
 771                        /* PIN = AA17->sys_clkreq        mode 0   -DO- */
 772                        __raw_writeb(0x0, base+0x136);
 773                } else if (cpu == CPU_2422) {
 774                        /* PIN = B3,  GPIO.0->nc,        mode 3,  set above (pun?)*/
 775                        /* PIN = B13, GPIO.cke1->nc,     mode 0,  set above, (pun?)*/
 776                        /* PIN = F1, GPIO.25->HSUSBxx    mode 3,  (for external HS USB)*/
 777                        /* PIN = H1, GPIO.26->HSUSBxx    mode 3,  (for external HS USB)*/
 778                        /* PIN = K1, GPMC_ncs6           mode 0,  (on board nand access)*/
 779                        __raw_writeb(0x0, base+0x92);
 780                        /* PIN = L2, GPMC_ncs67          mode 0,  (for external HS USB)*/
 781                        /* PIN = M1 (HSUSBOTG) */
 782                        /* PIN = P1, GPIO.35->MEN_POK    mode 3,  (menelaus powerok)-DO-*/
 783                        __raw_writeb(0x3, base+0x10c);
 784                        /* PIN = U32, (WLAN_CLKREQ) */
 785                        /* PIN = AA4, GPIO.15->KBC2,     mode 3,  -DO- */
 786                        __raw_writeb(0x3, base+0x30);
 787                        /* PIN = AA8, mDOC */
 788                        /* PIN = AA10, BT */
 789                        /* PIN = AA12, WLAN */
 790                        /* PIN = M18 GPIO.96->MMC2_WP    mode 3   -DO- */
 791                        __raw_writeb(0x3, base+0x10e);
 792                        /* PIN = N19 GPIO.98->WLAN_INT   mode 3   -DO- */
 793                        __raw_writeb(0x3, base+0x110);
 794                        /* PIN = J15 HHUSB */
 795                        /* PIN = H19 HSUSB */
 796                        /* PIN = W13, P13, R13, W16 ... */
 797                        /* PIN = V12 GPIO.25->I2C_CAMEN  mode 3   -DO- */
 798                        __raw_writeb(0x3, base+0xde);
 799                        /* PIN = W19 sys_nirq->MENELAUS_INT mode 0 -DO- */
 800                        __raw_writeb(0x0, base+0x12c);
 801                        /* PIN = AA17->sys_clkreq        mode 0   -DO- */
 802                        __raw_writeb(0x0, base+0x136);
 803                }
 804
 805        } else if (btype == BOARD_H4_SDP) {
 806                if (cpu == CPU_2420) {
 807                        /* PIN = B3,  GPIO.0->nc         mode 3,  set above (pun?)*/
 808                        /* PIN = B13, GPIO.cke1->nc,     mode 0,  set above, (pun?)*/
 809                        /* Pin = Y11 VLNQ */
 810                        /* Pin = AA4 VLNQ */
 811                        /* Pin = AA6 VLNQ */
 812                        /* Pin = AA8 VLNQ */
 813                        /* Pin = AA10 VLNQ */
 814                        /* Pin = AA12 VLNQ */
 815                        /* PIN = M18 GPIO.96->KBR5       mode 3   -DO- */
 816                        __raw_writeb(0x3, base+0x10e);
 817                        /* PIN = N19 GPIO.98->KBC6       mode 3   -DO- */
 818                        __raw_writeb(0x3, base+0x110);
 819                        /* PIN = J15 MDOC_nDMAREQ */
 820                        /* PIN = H19 GPIO.100->KBC2      mode 3   -DO- */
 821                        __raw_writeb(0x3, base+0x114);
 822                        /* PIN = W13, V12, P13, R13, W19, W16 ... */
 823                        /* PIN = AA17 sys_clkreq->bt_clk_req  mode 0  */
 824                } else if (cpu == CPU_2422) {
 825                        /* PIN = B3,  GPIO.0->MMC_CD,    mode 3,  set above */
 826                        /* PIN = B13, GPIO.38->wlan_int, mode 3,  (pun?)*/
 827                        /* Pin = Y11 VLNQ */
 828                        /* Pin = AA4 VLNQ */
 829                        /* Pin = AA6 VLNQ */
 830                        /* Pin = AA8 VLNQ */
 831                        /* Pin = AA10 VLNQ */
 832                        /* Pin = AA12 VLNQ */
 833                        /* PIN = M18 GPIO.96->KBR5       mode 3   -DO- */
 834                        __raw_writeb(0x3, base+0x10e);
 835                        /* PIN = N19 GPIO.98->KBC6       mode 3   -DO- */
 836                        __raw_writeb(0x3, base+0x110);
 837                        /* PIN = J15 MDOC_nDMAREQ */
 838                        /* PIN = H19 GPIO.100->KBC2      mode 3   -DO- */
 839                        __raw_writeb(0x3, base+0x114);
 840                        /* PIN = W13, V12, P13, R13, W19, W16 ... */
 841                        /* PIN = AA17 sys_clkreq->bt_clk_req  mode 0 */
 842                }
 843        }
 844}
 845
 846#ifdef CONFIG_CMD_NET
 847int board_eth_init(bd_t *bis)
 848{
 849        int rc = 0;
 850#ifdef CONFIG_LAN91C96
 851        rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
 852#endif
 853        return rc;
 854}
 855#endif
 856