1/* 2 * (C) Copyright 2011 3 * eInfochips Ltd. <www.einfochips.com> 4 * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com> 5 * 6 * (C) Copyright 2010 7 * Marvell Semiconductor <www.marvell.com> 8 * Contributor: Mahavir Jain <mjain@marvell.com> 9 * 10 * See file CREDITS for list of people who contributed to this 11 * project. 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of 16 * the License, or (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 26 * MA 02110-1301 USA 27 */ 28 29#ifndef __ARMADA100_FEC_H__ 30#define __ARMADA100_FEC_H__ 31 32#ifndef TRUE 33#define TRUE 1 34#endif 35#ifndef FALSE 36#define FALSE 0 37#endif 38 39#define PORT_NUM 0x0 40 41/* RX & TX descriptor command */ 42#define BUF_OWNED_BY_DMA (1<<31) 43 44/* RX descriptor status */ 45#define RX_EN_INT (1<<23) 46#define RX_FIRST_DESC (1<<17) 47#define RX_LAST_DESC (1<<16) 48#define RX_ERROR (1<<15) 49 50/* TX descriptor command */ 51#define TX_EN_INT (1<<23) 52#define TX_GEN_CRC (1<<22) 53#define TX_ZERO_PADDING (1<<18) 54#define TX_FIRST_DESC (1<<17) 55#define TX_LAST_DESC (1<<16) 56#define TX_ERROR (1<<15) 57 58/* smi register */ 59#define SMI_BUSY (1<<28) /* 0 - Write, 1 - Read */ 60#define SMI_R_VALID (1<<27) /* 0 - Write, 1 - Read */ 61#define SMI_OP_W (0<<26) /* Write operation */ 62#define SMI_OP_R (1<<26) /* Read operation */ 63 64#define HASH_ADD 0 65#define HASH_DELETE 1 66#define HASH_ADDR_TABLE_SIZE 0x4000 /* 16K (1/2K address - PCR_HS == 1) */ 67#define HOP_NUMBER 12 68 69#define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */ 70#define PHY_WAIT_MICRO_SECONDS 10 71 72#define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */ 73#define ETH_EXTRA_HEADER (6+6+2+4) 74 /* dest+src addr+protocol id+crc */ 75#define MAX_PKT_SIZE 1536 76 77 78/* Bit definitions of the SDMA Config Reg */ 79#define SDCR_BSZ_OFF 12 80#define SDCR_BSZ8 (3<<SDCR_BSZ_OFF) 81#define SDCR_BSZ4 (2<<SDCR_BSZ_OFF) 82#define SDCR_BSZ2 (1<<SDCR_BSZ_OFF) 83#define SDCR_BSZ1 (0<<SDCR_BSZ_OFF) 84#define SDCR_BLMR (1<<6) 85#define SDCR_BLMT (1<<7) 86#define SDCR_RIFB (1<<9) 87#define SDCR_RC_OFF 2 88#define SDCR_RC_MAX_RETRANS (0xf << SDCR_RC_OFF) 89 90/* SDMA_CMD */ 91#define SDMA_CMD_AT (1<<31) 92#define SDMA_CMD_TXDL (1<<24) 93#define SDMA_CMD_TXDH (1<<23) 94#define SDMA_CMD_AR (1<<15) 95#define SDMA_CMD_ERD (1<<7) 96 97 98/* Bit definitions of the Port Config Reg */ 99#define PCR_HS (1<<12) 100#define PCR_EN (1<<7) 101#define PCR_PM (1<<0) 102 103/* Bit definitions of the Port Config Extend Reg */ 104#define PCXR_2BSM (1<<28) 105#define PCXR_DSCP_EN (1<<21) 106#define PCXR_MFL_1518 (0<<14) 107#define PCXR_MFL_1536 (1<<14) 108#define PCXR_MFL_2048 (2<<14) 109#define PCXR_MFL_64K (3<<14) 110#define PCXR_FLP (1<<11) 111#define PCXR_PRIO_TX_OFF 3 112#define PCXR_TX_HIGH_PRI (7<<PCXR_PRIO_TX_OFF) 113 114/* 115 * * Bit definitions of the Interrupt Cause Reg 116 * * and Interrupt MASK Reg is the same 117 * */ 118#define ICR_RXBUF (1<<0) 119#define ICR_TXBUF_H (1<<2) 120#define ICR_TXBUF_L (1<<3) 121#define ICR_TXEND_H (1<<6) 122#define ICR_TXEND_L (1<<7) 123#define ICR_RXERR (1<<8) 124#define ICR_TXERR_H (1<<10) 125#define ICR_TXERR_L (1<<11) 126#define ICR_TX_UDR (1<<13) 127#define ICR_MII_CH (1<<28) 128 129#define ALL_INTS (ICR_TXBUF_H | ICR_TXBUF_L | ICR_TX_UDR |\ 130 ICR_TXERR_H | ICR_TXERR_L |\ 131 ICR_TXEND_H | ICR_TXEND_L |\ 132 ICR_RXBUF | ICR_RXERR | ICR_MII_CH) 133 134#define PHY_MASK 0x0000001f 135 136#define to_darmdfec(_kd) container_of(_kd, struct armdfec_device, dev) 137/* Size of a Tx/Rx descriptor used in chain list data structure */ 138#define ARMDFEC_RXQ_DESC_ALIGNED_SIZE \ 139 (((sizeof(struct rx_desc) / PKTALIGN) + 1) * PKTALIGN) 140 141#define RX_BUF_OFFSET 0x2 142#define RXQ 0x0 /* RX Queue 0 */ 143#define TXQ 0x1 /* TX Queue 1 */ 144 145struct addr_table_entry_t { 146 u32 lo; 147 u32 hi; 148}; 149 150/* Bit fields of a Hash Table Entry */ 151enum hash_table_entry { 152 HTEVALID = 1, 153 HTESKIP = 2, 154 HTERD = 4, 155 HTERDBIT = 2 156}; 157 158struct tx_desc { 159 u32 cmd_sts; /* Command/status field */ 160 u16 reserved; 161 u16 byte_cnt; /* buffer byte count */ 162 u8 *buf_ptr; /* pointer to buffer for this descriptor */ 163 struct tx_desc *nextdesc_p; /* Pointer to next descriptor */ 164}; 165 166struct rx_desc { 167 u32 cmd_sts; /* Descriptor command status */ 168 u16 byte_cnt; /* Descriptor buffer byte count */ 169 u16 buf_size; /* Buffer size */ 170 u8 *buf_ptr; /* Descriptor buffer pointer */ 171 struct rx_desc *nxtdesc_p; /* Next descriptor pointer */ 172}; 173 174/* 175 * Armada100 Fast Ethernet controller Registers 176 * Refer Datasheet Appendix A.22 177 */ 178struct armdfec_reg { 179 u32 phyadr; /* PHY Address */ 180 u32 pad1[3]; 181 u32 smi; /* SMI */ 182 u32 pad2[0xFB]; 183 u32 pconf; /* Port configuration */ 184 u32 pad3; 185 u32 pconf_ext; /* Port configuration extend */ 186 u32 pad4; 187 u32 pcmd; /* Port Command */ 188 u32 pad5; 189 u32 pstatus; /* Port Status */ 190 u32 pad6; 191 u32 spar; /* Serial Parameters */ 192 u32 pad7; 193 u32 htpr; /* Hash table pointer */ 194 u32 pad8; 195 u32 fcsal; /* Flow control source address low */ 196 u32 pad9; 197 u32 fcsah; /* Flow control source address high */ 198 u32 pad10; 199 u32 sdma_conf; /* SDMA configuration */ 200 u32 pad11; 201 u32 sdma_cmd; /* SDMA command */ 202 u32 pad12; 203 u32 ic; /* Interrupt cause */ 204 u32 iwc; /* Interrupt write to clear */ 205 u32 im; /* Interrupt mask */ 206 u32 pad13; 207 u32 *eth_idscpp[4]; /* Eth0 IP Differentiated Services Code 208 Point to Priority 0 Low */ 209 u32 eth_vlan_p; /* Eth0 VLAN Priority Tag to Priority */ 210 u32 pad14[3]; 211 struct rx_desc *rxfdp[4]; /* Ethernet First Rx Descriptor 212 Pointer */ 213 u32 pad15[4]; 214 struct rx_desc *rxcdp[4]; /* Ethernet Current Rx Descriptor 215 Pointer */ 216 u32 pad16[0x0C]; 217 struct tx_desc *txcdp[2]; /* Ethernet Current Tx Descriptor 218 Pointer */ 219}; 220 221struct armdfec_device { 222 struct eth_device dev; 223 struct armdfec_reg *regs; 224 struct tx_desc *p_txdesc; 225 struct rx_desc *p_rxdesc; 226 struct rx_desc *p_rxdesc_curr; 227 u8 *p_rxbuf; 228 u8 *p_aligned_txbuf; 229 u8 *htpr; /* hash pointer */ 230}; 231 232#endif /* __ARMADA100_FEC_H__ */ 233