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11#include <common.h>
12#include <malloc.h>
13#include <spi.h>
14
15#include <asm/blackfin.h>
16#include <asm/dma.h>
17#include <asm/gpio.h>
18#include <asm/portmux.h>
19#include <asm/mach-common/bits/spi.h>
20
21struct bfin_spi_slave {
22 struct spi_slave slave;
23 void *mmr_base;
24 u16 ctl, baud, flg;
25};
26
27#define MAKE_SPI_FUNC(mmr, off) \
28static inline void write_##mmr(struct bfin_spi_slave *bss, u16 val) { bfin_write16(bss->mmr_base + off, val); } \
29static inline u16 read_##mmr(struct bfin_spi_slave *bss) { return bfin_read16(bss->mmr_base + off); }
30MAKE_SPI_FUNC(SPI_CTL, 0x00)
31MAKE_SPI_FUNC(SPI_FLG, 0x04)
32MAKE_SPI_FUNC(SPI_STAT, 0x08)
33MAKE_SPI_FUNC(SPI_TDBR, 0x0c)
34MAKE_SPI_FUNC(SPI_RDBR, 0x10)
35MAKE_SPI_FUNC(SPI_BAUD, 0x14)
36
37#define to_bfin_spi_slave(s) container_of(s, struct bfin_spi_slave, slave)
38
39#define gpio_cs(cs) ((cs) - MAX_CTRL_CS)
40#ifdef CONFIG_BFIN_SPI_GPIO_CS
41# define is_gpio_cs(cs) ((cs) > MAX_CTRL_CS)
42#else
43# define is_gpio_cs(cs) 0
44#endif
45
46int spi_cs_is_valid(unsigned int bus, unsigned int cs)
47{
48 if (is_gpio_cs(cs))
49 return gpio_is_valid(gpio_cs(cs));
50 else
51 return (cs >= 1 && cs <= MAX_CTRL_CS);
52}
53
54void spi_cs_activate(struct spi_slave *slave)
55{
56 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
57
58 if (is_gpio_cs(slave->cs)) {
59 unsigned int cs = gpio_cs(slave->cs);
60 gpio_set_value(cs, bss->flg);
61 debug("%s: SPI_CS_GPIO:%x\n", __func__, gpio_get_value(cs));
62 } else {
63 write_SPI_FLG(bss,
64 (read_SPI_FLG(bss) &
65 ~((!bss->flg << 8) << slave->cs)) |
66 (1 << slave->cs));
67 debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
68 }
69
70 SSYNC();
71}
72
73void spi_cs_deactivate(struct spi_slave *slave)
74{
75 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
76
77 if (is_gpio_cs(slave->cs)) {
78 unsigned int cs = gpio_cs(slave->cs);
79 gpio_set_value(cs, !bss->flg);
80 debug("%s: SPI_CS_GPIO:%x\n", __func__, gpio_get_value(cs));
81 } else {
82 u16 flg;
83
84
85
86
87
88 flg = read_SPI_FLG(bss) | ((!bss->flg << 8) << slave->cs);
89 write_SPI_FLG(bss, flg);
90 SSYNC();
91 debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
92
93 flg &= ~(1 << slave->cs);
94 write_SPI_FLG(bss, flg);
95 debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
96 }
97
98 SSYNC();
99}
100
101void spi_init()
102{
103}
104
105#ifdef SPI_CTL
106# define SPI0_CTL SPI_CTL
107#endif
108
109#define SPI_PINS(n) \
110 [n] = { 0, P_SPI##n##_SCK, P_SPI##n##_MISO, P_SPI##n##_MOSI, 0 }
111static unsigned short pins[][5] = {
112#ifdef SPI0_CTL
113 SPI_PINS(0),
114#endif
115#ifdef SPI1_CTL
116 SPI_PINS(1),
117#endif
118#ifdef SPI2_CTL
119 SPI_PINS(2),
120#endif
121};
122
123#define SPI_CS_PINS(n) \
124 [n] = { \
125 P_SPI##n##_SSEL1, P_SPI##n##_SSEL2, P_SPI##n##_SSEL3, \
126 P_SPI##n##_SSEL4, P_SPI##n##_SSEL5, P_SPI##n##_SSEL6, \
127 P_SPI##n##_SSEL7, \
128 }
129static const unsigned short cs_pins[][7] = {
130#ifdef SPI0_CTL
131 SPI_CS_PINS(0),
132#endif
133#ifdef SPI1_CTL
134 SPI_CS_PINS(1),
135#endif
136#ifdef SPI2_CTL
137 SPI_CS_PINS(2),
138#endif
139};
140
141void spi_set_speed(struct spi_slave *slave, uint hz)
142{
143 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
144 ulong sclk;
145 u32 baud;
146
147 sclk = get_sclk();
148 baud = sclk / (2 * hz);
149
150 if (sclk % (2 * hz))
151 baud += 1;
152 if (baud < 2)
153 baud = 2;
154 else if (baud > (u16)-1)
155 baud = -1;
156 bss->baud = baud;
157}
158
159struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
160 unsigned int max_hz, unsigned int mode)
161{
162 struct bfin_spi_slave *bss;
163 u32 mmr_base;
164
165 if (!spi_cs_is_valid(bus, cs))
166 return NULL;
167
168 if (bus >= ARRAY_SIZE(pins) || pins[bus] == NULL) {
169 debug("%s: invalid bus %u\n", __func__, bus);
170 return NULL;
171 }
172 switch (bus) {
173#ifdef SPI0_CTL
174 case 0: mmr_base = SPI0_CTL; break;
175#endif
176#ifdef SPI1_CTL
177 case 1: mmr_base = SPI1_CTL; break;
178#endif
179#ifdef SPI2_CTL
180 case 2: mmr_base = SPI2_CTL; break;
181#endif
182 default: return NULL;
183 }
184
185 bss = malloc(sizeof(*bss));
186 if (!bss)
187 return NULL;
188
189 bss->slave.bus = bus;
190 bss->slave.cs = cs;
191 bss->mmr_base = (void *)mmr_base;
192 bss->ctl = SPE | MSTR | TDBR_CORE;
193 if (mode & SPI_CPHA) bss->ctl |= CPHA;
194 if (mode & SPI_CPOL) bss->ctl |= CPOL;
195 if (mode & SPI_LSB_FIRST) bss->ctl |= LSBF;
196 bss->flg = mode & SPI_CS_HIGH ? 1 : 0;
197 spi_set_speed(&bss->slave, max_hz);
198
199 debug("%s: bus:%i cs:%i mmr:%x ctl:%x baud:%i flg:%i\n", __func__,
200 bus, cs, mmr_base, bss->ctl, bss->baud, bss->flg);
201
202 return &bss->slave;
203}
204
205void spi_free_slave(struct spi_slave *slave)
206{
207 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
208 free(bss);
209}
210
211int spi_claim_bus(struct spi_slave *slave)
212{
213 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
214
215 debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
216
217 if (is_gpio_cs(slave->cs)) {
218 unsigned int cs = gpio_cs(slave->cs);
219 gpio_request(cs, "bfin-spi");
220 gpio_direction_output(cs, !bss->flg);
221 pins[slave->bus][0] = P_DONTCARE;
222 } else
223 pins[slave->bus][0] = cs_pins[slave->bus][slave->cs - 1];
224 peripheral_request_list(pins[slave->bus], "bfin-spi");
225
226 write_SPI_CTL(bss, bss->ctl);
227 write_SPI_BAUD(bss, bss->baud);
228 SSYNC();
229
230 return 0;
231}
232
233void spi_release_bus(struct spi_slave *slave)
234{
235 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
236
237 debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
238
239 peripheral_free_list(pins[slave->bus]);
240 if (is_gpio_cs(slave->cs))
241 gpio_free(gpio_cs(slave->cs));
242
243 write_SPI_CTL(bss, 0);
244 SSYNC();
245}
246
247#ifdef __ADSPBF54x__
248# define SPI_DMA_BASE DMA4_NEXT_DESC_PTR
249#elif defined(__ADSPBF533__) || defined(__ADSPBF532__) || defined(__ADSPBF531__) || \
250 defined(__ADSPBF538__) || defined(__ADSPBF539__)
251# define SPI_DMA_BASE DMA5_NEXT_DESC_PTR
252#elif defined(__ADSPBF561__)
253# define SPI_DMA_BASE DMA2_4_NEXT_DESC_PTR
254#elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__) || \
255 defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
256# define SPI_DMA_BASE DMA7_NEXT_DESC_PTR
257# elif defined(__ADSPBF50x__)
258# define SPI_DMA_BASE DMA6_NEXT_DESC_PTR
259#else
260# error "Please provide SPI DMA channel defines"
261#endif
262static volatile struct dma_register *dma = (void *)SPI_DMA_BASE;
263
264#ifndef CONFIG_BFIN_SPI_IDLE_VAL
265# define CONFIG_BFIN_SPI_IDLE_VAL 0xff
266#endif
267
268#ifdef CONFIG_BFIN_SPI_NO_DMA
269# define SPI_DMA 0
270#else
271# define SPI_DMA 1
272#endif
273
274static int spi_dma_xfer(struct bfin_spi_slave *bss, const u8 *tx, u8 *rx,
275 uint bytes)
276{
277 int ret = -1;
278 u16 ndsize, spi_config, dma_config;
279 struct dmasg dmasg[2];
280 const u8 *buf;
281
282 if (tx) {
283 debug("%s: doing half duplex TX\n", __func__);
284 buf = tx;
285 spi_config = TDBR_DMA;
286 dma_config = 0;
287 } else {
288 debug("%s: doing half duplex RX\n", __func__);
289 buf = rx;
290 spi_config = RDBR_DMA;
291 dma_config = WNR;
292 }
293
294 dmasg[0].start_addr = (unsigned long)buf;
295 dmasg[0].x_modify = 1;
296 dma_config |= WDSIZE_8 | DMAEN;
297 if (bytes <= 65536) {
298 blackfin_dcache_flush_invalidate_range(buf, buf + bytes);
299 ndsize = NDSIZE_5;
300 dmasg[0].cfg = NDSIZE_0 | dma_config | FLOW_STOP | DI_EN;
301 dmasg[0].x_count = bytes;
302 } else {
303 blackfin_dcache_flush_invalidate_range(buf, buf + 65536 - 1);
304 ndsize = NDSIZE_7;
305 dmasg[0].cfg = NDSIZE_5 | dma_config | FLOW_ARRAY | DMA2D;
306 dmasg[0].x_count = 0;
307 dmasg[0].y_count = bytes >> 16;
308 dmasg[0].y_modify = 1;
309 dmasg[1].start_addr = (unsigned long)(buf + (bytes & ~0xFFFF));
310 dmasg[1].cfg = NDSIZE_0 | dma_config | FLOW_STOP | DI_EN;
311 dmasg[1].x_count = bytes & 0xFFFF;
312 dmasg[1].x_modify = 1;
313 }
314
315 dma->cfg = 0;
316 dma->irq_status = DMA_DONE | DMA_ERR;
317 dma->curr_desc_ptr = dmasg;
318 write_SPI_CTL(bss, (bss->ctl & ~TDBR_CORE));
319 write_SPI_STAT(bss, -1);
320 SSYNC();
321
322 write_SPI_TDBR(bss, CONFIG_BFIN_SPI_IDLE_VAL);
323 dma->cfg = ndsize | FLOW_ARRAY | DMAEN;
324 write_SPI_CTL(bss, (bss->ctl & ~TDBR_CORE) | spi_config);
325 SSYNC();
326
327
328
329
330
331
332 if (bytes > 65536)
333 blackfin_dcache_flush_invalidate_range(buf + 65536, buf + bytes);
334
335 while (!(dma->irq_status & DMA_DONE))
336 if (ctrlc())
337 goto done;
338
339 dma->cfg = 0;
340
341 ret = 0;
342 done:
343 write_SPI_CTL(bss, bss->ctl);
344 return ret;
345}
346
347static int spi_pio_xfer(struct bfin_spi_slave *bss, const u8 *tx, u8 *rx,
348 uint bytes)
349{
350
351 while (bytes--) {
352 u8 value = (tx ? *tx++ : CONFIG_BFIN_SPI_IDLE_VAL);
353 debug("%s: tx:%x ", __func__, value);
354 write_SPI_TDBR(bss, value);
355 SSYNC();
356 while ((read_SPI_STAT(bss) & TXS))
357 if (ctrlc())
358 return -1;
359 while (!(read_SPI_STAT(bss) & SPIF))
360 if (ctrlc())
361 return -1;
362 while (!(read_SPI_STAT(bss) & RXS))
363 if (ctrlc())
364 return -1;
365 value = read_SPI_RDBR(bss);
366 if (rx)
367 *rx++ = value;
368 debug("rx:%x\n", value);
369 }
370
371 return 0;
372}
373
374int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
375 void *din, unsigned long flags)
376{
377 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
378 const u8 *tx = dout;
379 u8 *rx = din;
380 uint bytes = bitlen / 8;
381 int ret = 0;
382
383 debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__,
384 slave->bus, slave->cs, bitlen, bytes, flags);
385
386 if (bitlen == 0)
387 goto done;
388
389
390 if (bitlen % 8) {
391 flags |= SPI_XFER_END;
392 goto done;
393 }
394
395 if (flags & SPI_XFER_BEGIN)
396 spi_cs_activate(slave);
397
398
399 if (SPI_DMA && bytes > 6 && (!tx ))
400 ret = spi_dma_xfer(bss, tx, rx, bytes);
401 else
402 ret = spi_pio_xfer(bss, tx, rx, bytes);
403
404 done:
405 if (flags & SPI_XFER_END)
406 spi_cs_deactivate(slave);
407
408 return ret;
409}
410
