1/* 2 * Copyright (C) Freescale Semiconductor, Inc. 2006. 3 * Author: Jason Jin<Jason.jin@freescale.com> 4 * Zhang Wei<wei.zhang@freescale.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 * 24 */ 25#ifndef _AHCI_H_ 26#define _AHCI_H_ 27 28#include <pci.h> 29 30#define AHCI_PCI_BAR 0x24 31#define AHCI_MAX_SG 56 /* hardware max is 64K */ 32#define AHCI_CMD_SLOT_SZ 32 33#define AHCI_MAX_CMD_SLOT 32 34#define AHCI_RX_FIS_SZ 256 35#define AHCI_CMD_TBL_HDR 0x80 36#define AHCI_CMD_TBL_CDB 0x40 37#define AHCI_CMD_TBL_SZ AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16) 38#define AHCI_PORT_PRIV_DMA_SZ (AHCI_CMD_SLOT_SZ * AHCI_MAX_CMD_SLOT + \ 39 AHCI_CMD_TBL_SZ + AHCI_RX_FIS_SZ) 40#define AHCI_CMD_ATAPI (1 << 5) 41#define AHCI_CMD_WRITE (1 << 6) 42#define AHCI_CMD_PREFETCH (1 << 7) 43#define AHCI_CMD_RESET (1 << 8) 44#define AHCI_CMD_CLR_BUSY (1 << 10) 45 46#define RX_FIS_D2H_REG 0x40 /* offset of D2H Register FIS data */ 47 48/* Global controller registers */ 49#define HOST_CAP 0x00 /* host capabilities */ 50#define HOST_CTL 0x04 /* global host control */ 51#define HOST_IRQ_STAT 0x08 /* interrupt status */ 52#define HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */ 53#define HOST_VERSION 0x10 /* AHCI spec. version compliancy */ 54 55/* HOST_CTL bits */ 56#define HOST_RESET (1 << 0) /* reset controller; self-clear */ 57#define HOST_IRQ_EN (1 << 1) /* global IRQ enable */ 58#define HOST_AHCI_EN (1 << 31) /* AHCI enabled */ 59 60/* Registers for each SATA port */ 61#define PORT_LST_ADDR 0x00 /* command list DMA addr */ 62#define PORT_LST_ADDR_HI 0x04 /* command list DMA addr hi */ 63#define PORT_FIS_ADDR 0x08 /* FIS rx buf addr */ 64#define PORT_FIS_ADDR_HI 0x0c /* FIS rx buf addr hi */ 65#define PORT_IRQ_STAT 0x10 /* interrupt status */ 66#define PORT_IRQ_MASK 0x14 /* interrupt enable/disable mask */ 67#define PORT_CMD 0x18 /* port command */ 68#define PORT_TFDATA 0x20 /* taskfile data */ 69#define PORT_SIG 0x24 /* device TF signature */ 70#define PORT_CMD_ISSUE 0x38 /* command issue */ 71#define PORT_SCR 0x28 /* SATA phy register block */ 72#define PORT_SCR_STAT 0x28 /* SATA phy register: SStatus */ 73#define PORT_SCR_CTL 0x2c /* SATA phy register: SControl */ 74#define PORT_SCR_ERR 0x30 /* SATA phy register: SError */ 75#define PORT_SCR_ACT 0x34 /* SATA phy register: SActive */ 76 77/* PORT_IRQ_{STAT,MASK} bits */ 78#define PORT_IRQ_COLD_PRES (1 << 31) /* cold presence detect */ 79#define PORT_IRQ_TF_ERR (1 << 30) /* task file error */ 80#define PORT_IRQ_HBUS_ERR (1 << 29) /* host bus fatal error */ 81#define PORT_IRQ_HBUS_DATA_ERR (1 << 28) /* host bus data error */ 82#define PORT_IRQ_IF_ERR (1 << 27) /* interface fatal error */ 83#define PORT_IRQ_IF_NONFATAL (1 << 26) /* interface non-fatal error */ 84#define PORT_IRQ_OVERFLOW (1 << 24) /* xfer exhausted available S/G */ 85#define PORT_IRQ_BAD_PMP (1 << 23) /* incorrect port multiplier */ 86 87#define PORT_IRQ_PHYRDY (1 << 22) /* PhyRdy changed */ 88#define PORT_IRQ_DEV_ILCK (1 << 7) /* device interlock */ 89#define PORT_IRQ_CONNECT (1 << 6) /* port connect change status */ 90#define PORT_IRQ_SG_DONE (1 << 5) /* descriptor processed */ 91#define PORT_IRQ_UNK_FIS (1 << 4) /* unknown FIS rx'd */ 92#define PORT_IRQ_SDB_FIS (1 << 3) /* Set Device Bits FIS rx'd */ 93#define PORT_IRQ_DMAS_FIS (1 << 2) /* DMA Setup FIS rx'd */ 94#define PORT_IRQ_PIOS_FIS (1 << 1) /* PIO Setup FIS rx'd */ 95#define PORT_IRQ_D2H_REG_FIS (1 << 0) /* D2H Register FIS rx'd */ 96 97#define PORT_IRQ_FATAL PORT_IRQ_TF_ERR | PORT_IRQ_HBUS_ERR \ 98 | PORT_IRQ_HBUS_DATA_ERR | PORT_IRQ_IF_ERR 99 100#define DEF_PORT_IRQ PORT_IRQ_FATAL | PORT_IRQ_PHYRDY \ 101 | PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE \ 102 | PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS \ 103 | PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS \ 104 | PORT_IRQ_D2H_REG_FIS 105 106/* PORT_CMD bits */ 107#define PORT_CMD_ATAPI (1 << 24) /* Device is ATAPI */ 108#define PORT_CMD_LIST_ON (1 << 15) /* cmd list DMA engine running */ 109#define PORT_CMD_FIS_ON (1 << 14) /* FIS DMA engine running */ 110#define PORT_CMD_FIS_RX (1 << 4) /* Enable FIS receive DMA engine */ 111#define PORT_CMD_CLO (1 << 3) /* Command list override */ 112#define PORT_CMD_POWER_ON (1 << 2) /* Power up device */ 113#define PORT_CMD_SPIN_UP (1 << 1) /* Spin up device */ 114#define PORT_CMD_START (1 << 0) /* Enable port DMA engine */ 115 116#define PORT_CMD_ICC_ACTIVE (0x1 << 28) /* Put i/f in active state */ 117#define PORT_CMD_ICC_PARTIAL (0x2 << 28) /* Put i/f in partial state */ 118#define PORT_CMD_ICC_SLUMBER (0x6 << 28) /* Put i/f in slumber state */ 119 120#define AHCI_MAX_PORTS 32 121 122/* SETFEATURES stuff */ 123#define SETFEATURES_XFER 0x03 124#define XFER_UDMA_7 0x47 125#define XFER_UDMA_6 0x46 126#define XFER_UDMA_5 0x45 127#define XFER_UDMA_4 0x44 128#define XFER_UDMA_3 0x43 129#define XFER_UDMA_2 0x42 130#define XFER_UDMA_1 0x41 131#define XFER_UDMA_0 0x40 132#define XFER_MW_DMA_2 0x22 133#define XFER_MW_DMA_1 0x21 134#define XFER_MW_DMA_0 0x20 135#define XFER_SW_DMA_2 0x12 136#define XFER_SW_DMA_1 0x11 137#define XFER_SW_DMA_0 0x10 138#define XFER_PIO_4 0x0C 139#define XFER_PIO_3 0x0B 140#define XFER_PIO_2 0x0A 141#define XFER_PIO_1 0x09 142#define XFER_PIO_0 0x08 143#define XFER_PIO_SLOW 0x00 144 145#define ATA_FLAG_SATA (1 << 3) 146#define ATA_FLAG_NO_LEGACY (1 << 4) /* no legacy mode check */ 147#define ATA_FLAG_MMIO (1 << 6) /* use MMIO, not PIO */ 148#define ATA_FLAG_SATA_RESET (1 << 7) /* (obsolete) use COMRESET */ 149#define ATA_FLAG_PIO_DMA (1 << 8) /* PIO cmds via DMA */ 150#define ATA_FLAG_NO_ATAPI (1 << 11) /* No ATAPI support */ 151 152struct ahci_cmd_hdr { 153 u32 opts; 154 u32 status; 155 u32 tbl_addr; 156 u32 tbl_addr_hi; 157 u32 reserved[4]; 158}; 159 160struct ahci_sg { 161 u32 addr; 162 u32 addr_hi; 163 u32 reserved; 164 u32 flags_size; 165}; 166 167struct ahci_ioports { 168 u32 cmd_addr; 169 u32 scr_addr; 170 u32 port_mmio; 171 struct ahci_cmd_hdr *cmd_slot; 172 struct ahci_sg *cmd_tbl_sg; 173 u32 cmd_tbl; 174 u32 rx_fis; 175}; 176 177struct ahci_probe_ent { 178 pci_dev_t dev; 179 struct ahci_ioports port[AHCI_MAX_PORTS]; 180 u32 n_ports; 181 u32 hard_port_no; 182 u32 host_flags; 183 u32 host_set_flags; 184 u32 mmio_base; 185 u32 pio_mask; 186 u32 udma_mask; 187 u32 flags; 188 u32 cap; /* cache of HOST_CAP register */ 189 u32 port_map; /* cache of HOST_PORTS_IMPL reg */ 190 u32 link_port_map; /*linkup port map*/ 191}; 192 193int ahci_init(u32 base); 194 195#endif 196