1/* 2 * (C) Copyright 2001 3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* 25 * board/config.h - configuration options, board specific 26 */ 27 28#ifndef __CONFIG_H 29#define __CONFIG_H 30 31/* 32 * High Level Configuration Options 33 * (easy to change) 34 */ 35 36#define CONFIG_405CR 1 /* This is a PPC405CR CPU */ 37#define CONFIG_4xx 1 /* ...member of PPC4xx family */ 38#define CONFIG_CANBT 1 /* ...on a CANBT board */ 39 40#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 41 42#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ 43 44#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ 45 46#define CONFIG_BAUDRATE 115200 47#define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */ 48 49#undef CONFIG_BOOTARGS 50#define CONFIG_BOOTCOMMAND \ 51 "setenv bootargs root=/dev/ram rw console=ttyS0,115200; " \ 52 "bootm ffe00000 ffe80000" 53 54#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 55#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 56 57#undef CONFIG_PCI_PNP /* no pci plug-and-play */ 58 59#define CONFIG_PHY_ADDR 0 /* PHY address */ 60 61 62/* 63 * BOOTP options 64 */ 65#define CONFIG_BOOTP_BOOTFILESIZE 66#define CONFIG_BOOTP_BOOTPATH 67#define CONFIG_BOOTP_GATEWAY 68#define CONFIG_BOOTP_HOSTNAME 69 70 71/* 72 * Command line configuration. 73 */ 74#include <config_cmd_default.h> 75 76#define CONFIG_CMD_IRQ 77#define CONFIG_CMD_EEPROM 78 79#undef CONFIG_CMD_NET 80#undef CONFIG_CMD_NFS 81 82#undef CONFIG_WATCHDOG /* watchdog disabled */ 83 84#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ 85 86/* 87 * Miscellaneous configurable options 88 */ 89#define CONFIG_SYS_LONGHELP /* undef to save memory */ 90#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 91#if defined(CONFIG_CMD_KGDB) 92#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 93#else 94#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 95#endif 96#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 97#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 98#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 99 100#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ 101 102#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 103#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 104 105#define CONFIG_CONS_INDEX 1 /* Use UART0 */ 106#define CONFIG_SYS_NS16550 107#define CONFIG_SYS_NS16550_SERIAL 108#define CONFIG_SYS_NS16550_REG_SIZE 1 109#define CONFIG_SYS_NS16550_CLK get_serial_clock() 110 111#define CONFIG_SYS_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */ 112 113/* The following table includes the supported baudrates */ 114#define CONFIG_SYS_BAUDRATE_TABLE \ 115 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ 116 57600, 115200, 230400, 460800, 921600 } 117 118#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 119#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ 120 121#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 122 123#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ 124 125/*----------------------------------------------------------------------- 126 * Start addresses for the final memory configuration 127 * (Set up by the startup code) 128 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 129 */ 130#define CONFIG_SYS_SDRAM_BASE 0x00000000 131#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE 132#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 133#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1) 134#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ 135 136/* 137 * For booting Linux, the board info and command line data 138 * have to be in the first 8 MB of memory, since this is 139 * the maximum mapped by the Linux kernel during initialization. 140 */ 141#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 142/*----------------------------------------------------------------------- 143 * FLASH organization 144 */ 145#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 146#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 147 148#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 149#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 150 151#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ 152#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ 153#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ 154/* 155 * The following defines are added for buggy IOP480 byte interface. 156 * All other boards should use the standard values (CPCI405 etc.) 157 */ 158#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ 159#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ 160#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ 161 162#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ 163 164#if 0 /* Use FLASH for environment variables */ 165 166#define CONFIG_ENV_IS_IN_FLASH 1 167#define CONFIG_ENV_OFFSET 0x00010000 /* Offset of Environment Sector */ 168#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ 169 170#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */ 171 172#else /* Use EEPROM for environment variables */ 173 174#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ 175#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ 176#define CONFIG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */ 177 /* total size of a CAT24WC08 is 1024 bytes */ 178#endif 179 180/*----------------------------------------------------------------------- 181 * I2C EEPROM (CAT24WC08) for environment 182 */ 183#define CONFIG_HARD_I2C /* I2C with hardware support */ 184#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ 185#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 186#define CONFIG_SYS_I2C_SLAVE 0x7F 187 188#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ 189#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ 190/* mask of address bits that overflow into the "EEPROM chip address" */ 191#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 192 193/* 194 * Init Memory Controller: 195 * 196 * BR0/1 and OR0/1 (FLASH) 197 */ 198 199#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ 200#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ 201 202/*----------------------------------------------------------------------- 203 * External Bus Controller (EBC) Setup 204 */ 205 206/* Memory Bank 0 (Flash Bank 0) initialization */ 207#define CONFIG_SYS_EBC_PB0AP 0x92015480 208#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ 209 210/* Memory Bank 1 (CAN/USB) initialization */ 211#define CONFIG_SYS_EBC_PB1AP 0x010053C0 /* enable Ready, BEM=1 */ 212#define CONFIG_SYS_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ 213 214/* Memory Bank 2 (Misc-IO/LEDs) initialization */ 215#define CONFIG_SYS_EBC_PB2AP 0x000004c0 /* no Ready, BEM=1 */ 216#define CONFIG_SYS_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */ 217 218/* Memory Bank 3 (CAN Features) initialization */ 219#define CONFIG_SYS_EBC_PB3AP 0x80000040 /* no Ready, BEM=1 */ 220#define CONFIG_SYS_EBC_PB3CR 0xF021C000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=32bit */ 221 222/*----------------------------------------------------------------------- 223 * Definitions for initial stack pointer and data area (in RAM) 224 */ 225#define CONFIG_SYS_INIT_RAM_ADDR 0x00ef0000 /* inside of SDRAM */ 226#define CONFIG_SYS_INIT_RAM_SIZE 0x0f00 /* Size of used area in RAM */ 227#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 228#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 229 230#endif /* __CONFIG_H */ 231