1/* 2 * (C) Copyright 2001 3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* 25 * board/config.h - configuration options, board specific 26 */ 27 28/************************************************************************* 29 * (c) 2002 Datentechnik AG - Project: Dino 30 * 31 * 32 * $Id: DB64360.h,v 1.3 2003/04/26 04:58:13 brad Exp $ 33 * 34 ************************************************************************/ 35 36/************************************************************************* 37 * 38 * History: 39 * 40 * $Log: DB64360.h,v $ 41 * Revision 1.3 2003/04/26 04:58:13 brad 42 * Cosmetic changes and compiler warning cleanups 43 * 44 * Revision 1.2 2003/04/23 15:48:15 ingo 45 * mem. map output added 46 * 47 * Revision 1.1 2003/04/17 09:31:42 ias 48 * keymile changes 17_04_2003 49 * 50 * Revision 1.10 2003/03/06 12:25:04 ias 51 * 750 FX CPU HID settings updated 52 * 53 * Revision 1.9 2003/03/03 16:14:36 ias 54 * cleanup compiler warnings of printf fuctions 55 * 56 * Revision 1.8 2003/03/03 15:11:44 ias 57 * Marvell MPSC-UART is working 58 * 59 * Revision 1.7 2003/02/26 12:15:45 ssu 60 * adapted default parameters to new board flash address 61 * 62 * Revision 1.6 2003/02/25 14:55:42 ssu 63 * changed default environment parameters 64 * 65 * Revision 1.5 2003/02/21 17:14:23 ias 66 * added extended SPD handling 67 * 68 * Revision 1.4 2003/01/14 09:16:08 ias 69 * PPCBoot for Marvel Beta 0.9 70 * 71 * Revision 1.3 2002/12/03 13:56:26 ias 72 * Environment in flash support added 73 * 74 * Revision 1.2 2002/11/29 16:53:29 ias 75 * Flash support for STM added 76 * 77 * Revision 1.1 2002/11/29 13:36:31 ias 78 * Revision 0.1 of PPCBOOT (1.1.5) for Marvell DB64360 IBM750FX Board 79 * - working DDRRAM (only 32MByte of 128MB Modul) 80 * - working I2C Driver for SPD EEPROM read 81 * - working DUART 16650 for Serial Console 82 * - working "console" 83 * 84 * 85 * 86 ************************************************************************/ 87 88#ifndef __CONFIG_H 89#define __CONFIG_H 90 91/* This define must be before the core.h include */ 92#define CONFIG_DB64360 1 /* this is an DB64360 board */ 93 94#ifndef __ASSEMBLY__ 95#include "../board/Marvell/include/core.h" 96#endif 97 98/*-----------------------------------------------------*/ 99/* #include "../board/db64360/local.h" */ 100#ifndef __LOCAL_H 101#define __LOCAL_H 102 103/* first ethernet */ 104#define CONFIG_ETHADDR 64:36:00:00:00:01 105 /* next two ethernet hwaddrs */ 106#define CONFIG_HAS_ETH1 107#define CONFIG_ETH1ADDR 64:36:00:00:00:02 108/* in the atlantis 64360 we have only 2 ETH port on the board, 109if we use PCI it has its own MAC addr */ 110 111#define CONFIG_ENV_OVERWRITE 112#endif /* __CONFIG_H */ 113 114/* 115 * High Level Configuration Options 116 * (easy to change) 117 */ 118 119#define CONFIG_74xx /* we have a 750FX (override local.h) */ 120 121#define CONFIG_DB64360 1 /* this is an DB64360 board */ 122 123#define CONFIG_SYS_TEXT_BASE 0xfff00000 124 125#define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */ 126/*ronen - we don't use the global CONFIG_ECC, since in the global ecc we initialize the 127 DRAM for ECC in the phase we are relocating to it, which isn't so sufficient. 128 so we will define our ECC CONFIG and initilize the DRAM for ECC in the DRAM initialization phase, 129 see sdram_init.c */ 130#undef CONFIG_ECC /* enable ECC support */ 131#define CONFIG_MV64360_ECC 132 133/* which initialization functions to call for this board */ 134#define CONFIG_MISC_INIT_R /* initialize the icache L1 */ 135#define CONFIG_BOARD_EARLY_INIT_F 136 137#define CONFIG_SYS_BOARD_NAME "DB64360" 138#define CONFIG_IDENT_STRING "Marvell DB64360 (1.1)" 139 140/*#define CONFIG_SYS_HUSH_PARSER */ 141#undef CONFIG_SYS_HUSH_PARSER 142 143 144/* 145 * The following defines let you select what serial you want to use 146 * for your console driver. 147 * 148 * what to do: 149 * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial 150 * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1 151 * to 0 below. 152 * 153 * to use the MPSC, #define CONFIG_MPSC. If you have wired up another 154 * mpsc channel, change CONFIG_MPSC_PORT to the desired value. 155 */ 156 157#define CONFIG_MPSC_PORT 0 158 159/* to change the default ethernet port, use this define (options: 0, 1, 2) */ 160#define MV_ETH_DEVS 2 161 162/* #undef CONFIG_ETHER_PORT_MII */ 163#if 0 164#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ 165#else 166#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ 167#endif 168#define CONFIG_ZERO_BOOTDELAY_CHECK 169 170 171#undef CONFIG_BOOTARGS 172/*#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" */ 173 174/* ronen - autoboot using tftp */ 175#if (CONFIG_BOOTDELAY >= 0) 176#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 uImage;\ 177 setenv bootargs ${bootargs} ${bootargs_root} nfsroot=${serverip}:${rootpath} \ 178 ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000; " 179 180#define CONFIG_BOOTARGS "console=ttyS0,115200" 181 182#endif 183 184/* ronen - the u-boot.bin should be ~0x30000 bytes */ 185#define CONFIG_EXTRA_ENV_SETTINGS \ 186 "burn_uboot_sep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF4ffff; \ 187cp.b 100000 FFF00000 0x40000;protect on 1:0-4;\0" \ 188 "burn_uboot_dep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF7ffff; \ 189cp.b 100000 FFF00000 0x40000;protect on 1:0-7;\0" \ 190 "bootargs_root=root=/dev/nfs rw\0" \ 191 "bootargs_end=:::DB64360:eth0:none \0"\ 192 "ethprime=mv_enet0\0"\ 193 "standalone=fsload 0x400000 uImage;setenv bootargs ${bootargs} root=/dev/mtdblock/0 rw \ 194ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0" 195 196/* --------------------------------------------------------------------------------------------------------------- */ 197/* New bootcommands for Marvell DB64360 c 2002 Ingo Assmus */ 198 199#define CONFIG_IPADDR 10.2.40.90 200 201#define CONFIG_SERIAL "No. 1" 202#define CONFIG_SERVERIP 10.2.1.126 203#define CONFIG_ROOTPATH "/mnt/yellow_dog_mini" 204 205 206#define CONFIG_TESTDRAMDATA y 207#define CONFIG_TESTDRAMADDRESS n 208#define CONFIG_TESETDRAMWALK n 209 210/* --------------------------------------------------------------------------------------------------------------- */ 211 212#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ 213#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */ 214 215#undef CONFIG_WATCHDOG /* watchdog disabled */ 216#undef CONFIG_ALTIVEC /* undef to disable */ 217 218/* 219 * BOOTP options 220 */ 221#define CONFIG_BOOTP_SUBNETMASK 222#define CONFIG_BOOTP_GATEWAY 223#define CONFIG_BOOTP_HOSTNAME 224#define CONFIG_BOOTP_BOOTPATH 225#define CONFIG_BOOTP_BOOTFILESIZE 226 227 228/* 229 * JFFS2 partitions 230 * 231 */ 232/* No command line, one static partition, whole device */ 233#undef CONFIG_CMD_MTDPARTS 234#define CONFIG_JFFS2_DEV "nor1" 235#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF 236#define CONFIG_JFFS2_PART_OFFSET 0x00000000 237 238/* mtdparts command line support */ 239 240/* Use first bank for JFFS2, second bank contains U-Boot. 241 * 242 * Note: fake mtd_id's used, no linux mtd map file. 243 */ 244/* 245#define CONFIG_CMD_MTDPARTS 246#define MTDIDS_DEFAULT "nor1=db64360-1" 247#define MTDPARTS_DEFAULT "mtdparts=db64360-1:-(jffs2)" 248*/ 249 250 251/* 252 * Command line configuration. 253 */ 254#include <config_cmd_default.h> 255 256#define CONFIG_CMD_ASKENV 257#define CONFIG_CMD_I2C 258#define CONFIG_CMD_EEPROM 259#define CONFIG_CMD_CACHE 260#define CONFIG_CMD_JFFS2 261#define CONFIG_CMD_PCI 262#define CONFIG_CMD_NET 263 264 265/* 266 * Miscellaneous configurable options 267 */ 268#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 269#define CONFIG_SYS_I2C_MULTI_EEPROMS 270#define CONFIG_SYS_I2C_SPEED 40000 /* I2C speed default */ 271 272/* #define CONFIG_SYS_GT_DUAL_CPU also for JTAG even with one cpu */ 273#define CONFIG_SYS_LONGHELP /* undef to save memory */ 274#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 275#if defined(CONFIG_CMD_KGDB) 276#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 277#else 278#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 279#endif 280#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 281#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 282#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 283 284/*#define CONFIG_SYS_MEMTEST_START 0x00400000 memtest works on */ 285/*#define CONFIG_SYS_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */ 286/*#define CONFIG_SYS_MEMTEST_END 0x07c00000 4 ... 124 MB in DRAM */ 287 288/* 289#define CONFIG_SYS_DRAM_TEST 290 * DRAM tests 291 * CONFIG_SYS_DRAM_TEST - enables the following tests. 292 * 293 * CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines 294 * Environment variable 'test_dram_data' must be 295 * set to 'y'. 296 * CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely 297 * addressable. Environment variable 298 * 'test_dram_address' must be set to 'y'. 299 * CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test. 300 * This test takes about 6 minutes to test 64 MB. 301 * Environment variable 'test_dram_walk' must be 302 * set to 'y'. 303 */ 304#define CONFIG_SYS_DRAM_TEST 305#if defined(CONFIG_SYS_DRAM_TEST) 306#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ 307/* #define CONFIG_SYS_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */ 308#define CONFIG_SYS_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ 309#define CONFIG_SYS_DRAM_TEST_DATA 310#define CONFIG_SYS_DRAM_TEST_ADDRESS 311#define CONFIG_SYS_DRAM_TEST_WALK 312#endif /* CONFIG_SYS_DRAM_TEST */ 313 314#undef CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */ 315#undef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */ 316 317#define CONFIG_SYS_LOAD_ADDR 0x00400000 /* default load address */ 318 319#define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */ 320/*ronen - this the Sys clock (cpu bus,internal dram and SDRAM) */ 321#define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */ 322 323#define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */ 324#define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 400MHZ -> 5.0 ns, for 133MHZ -> 7.50 ns */ 325 326/*ronen - this is the Tclk (MV64360 core) */ 327#define CONFIG_SYS_TCLK 133000000 328 329 330#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } 331 332#define CONFIG_SYS_750FX_HID0 0x8000c084 333#define CONFIG_SYS_750FX_HID1 0x54800000 334#define CONFIG_SYS_750FX_HID2 0x00000000 335 336/* 337 * Low Level Configuration Settings 338 * (address mappings, register initial values, etc.) 339 * You should know what you are doing if you make changes here. 340 */ 341 342/*----------------------------------------------------------------------- 343 * Definitions for initial stack pointer and data area 344 */ 345 346/* 347 * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS 348 * To an unused memory region. The stack will remain in cache until RAM 349 * is initialized 350*/ 351#define CONFIG_SYS_INIT_RAM_LOCK 352#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* unused memory region */ 353#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 354#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 355 356#define RELOCATE_INTERNAL_RAM_ADDR 357#ifdef RELOCATE_INTERNAL_RAM_ADDR 358 #define CONFIG_SYS_INTERNAL_RAM_ADDR 0xf8000000 359#endif 360 361/*----------------------------------------------------------------------- 362 * Start addresses for the final memory configuration 363 * (Set up by the startup code) 364 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 365 */ 366#define CONFIG_SYS_SDRAM_BASE 0x00000000 367/* Dummies for BAT 4-7 */ 368#define CONFIG_SYS_SDRAM1_BASE 0x10000000 /* each 256 MByte */ 369#define CONFIG_SYS_SDRAM2_BASE 0x20000000 370#define CONFIG_SYS_SDRAM3_BASE 0x30000000 371#define CONFIG_SYS_SDRAM4_BASE 0x40000000 372#define CONFIG_SYS_FLASH_BASE 0xfff00000 373 374#define CONFIG_SYS_DFL_BOOTCS_BASE 0xff800000 375#define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS*/ 376 377#define BRIDGE_REG_BASE_BOOTM 0xfbe00000 /* this paramaters are used when booting the linux kernel */ 378#define UART_BASE_BOOTM 0xfbb00000 /* in order to be sync with the kernel parameters. */ 379#define PCI0_IO_BASE_BOOTM 0xfd000000 380 381#define CONFIG_SYS_RESET_ADDRESS 0xfff00100 382#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 383#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 384#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ 385 386/* areas to map different things with the GT in physical space */ 387#define CONFIG_SYS_DRAM_BANKS 4 388 389/* What to put in the bats. */ 390#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000 391 392/* Peripheral Device section */ 393 394/*******************************************************/ 395/* We have on the db64360 Board : */ 396/* GT-Chipset Register Area */ 397/* GT-Chipset internal SRAM 256k */ 398/* SRAM on external device module */ 399/* Real time clock on external device module */ 400/* dobble UART on external device module */ 401/* Data flash on external device module */ 402/* Boot flash on external device module */ 403/*******************************************************/ 404#define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ 405#define CONFIG_SYS_DB64360_RESET_ADDR 0x14000000 /* After power on Reset the DB64360 is here */ 406 407/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ 408#define CONFIG_SYS_GT_REGS 0xf1000000 /* GT Registers will be mapped here */ 409#define CONFIG_SYS_DEV_BASE 0xfc000000 /* GT Devices CS start here */ 410 411#define CONFIG_SYS_DEV0_SPACE CONFIG_SYS_DEV_BASE /* DEV_CS0 device modul sram */ 412#define CONFIG_SYS_DEV1_SPACE (CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE) /* DEV_CS1 device modul real time clock (rtc) */ 413#define CONFIG_SYS_DEV2_SPACE (CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE) /* DEV_CS2 device modul doubel uart (duart) */ 414#define CONFIG_SYS_DEV3_SPACE (CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE) /* DEV_CS3 device modul large flash */ 415 416#define CONFIG_SYS_DEV0_SIZE _8M /* db64360 sram @ 0xfc00.0000 */ 417#define CONFIG_SYS_DEV1_SIZE _8M /* db64360 rtc @ 0xfc80.0000 */ 418#define CONFIG_SYS_DEV2_SIZE _16M /* db64360 duart @ 0xfd00.0000 */ 419#define CONFIG_SYS_DEV3_SIZE _16M /* db64360 flash @ 0xfe00.0000 */ 420/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ 421 422/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */ 423#define CONFIG_SYS_DEV0_PAR 0x8FEFFFFF /* 32Bit sram */ 424#define CONFIG_SYS_DEV1_PAR 0x8FCFFFFF /* 8Bit rtc */ 425#define CONFIG_SYS_DEV2_PAR 0x8FCFFFFF /* 8Bit duart */ 426#define CONFIG_SYS_8BIT_BOOT_PAR 0x8FCFFFFF /* 8Bit flash */ 427#define CONFIG_SYS_32BIT_BOOT_PAR 0x8FEFFFFF /* 32Bit flash */ 428 429 /* c 4 a 8 2 4 1 c */ 430 /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ 431 /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ 432 /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */ 433 /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */ 434 435 436/* ronen - update MPP Control MV64360*/ 437#define CONFIG_SYS_MPP_CONTROL_0 0x02222222 438#define CONFIG_SYS_MPP_CONTROL_1 0x11333011 439#define CONFIG_SYS_MPP_CONTROL_2 0x40431111 440#define CONFIG_SYS_MPP_CONTROL_3 0x00000044 441 442/*# define CONFIG_SYS_SERIAL_PORT_MUX 0x00000102 0=hiZ 1=MPSC0 2=ETH 0 and 2 RMII */ 443 444 445# define CONFIG_SYS_GPP_LEVEL_CONTROL 0x2c600000 /* 1111 1001 0000 1111 1100 0000 0000 0000*/ 446 /* gpp[31] gpp[30] gpp[29] gpp[28] */ 447 /* gpp[27] gpp[24]*/ 448 /* gpp[19:14] */ 449 450/* setup new config_value for MV64360 DDR-RAM !! */ 451# define CONFIG_SYS_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/ 452 453#define CONFIG_SYS_DUART_IO CONFIG_SYS_DEV2_SPACE 454#define CONFIG_SYS_DUART_CHAN 1 /* channel to use for console */ 455#define CONFIG_SYS_INIT_CHAN1 456#define CONFIG_SYS_INIT_CHAN2 457 458#define SRAM_BASE CONFIG_SYS_DEV0_SPACE 459#define SRAM_SIZE 0x00100000 /* 1 MB of sram */ 460 461 462/*----------------------------------------------------------------------- 463 * PCI stuff 464 *----------------------------------------------------------------------- 465 */ 466 467#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ 468#define PCI_HOST_FORCE 1 /* configure as pci host */ 469#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ 470 471#define CONFIG_PCI /* include pci support */ 472#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ 473#define CONFIG_PCI_PNP /* do pci plug-and-play */ 474#define CONFIG_EEPRO100 /* ronen - Support for Intel 82557/82559/82559ER chips */ 475 476/* PCI MEMORY MAP section */ 477#define CONFIG_SYS_PCI0_MEM_BASE 0x80000000 478#define CONFIG_SYS_PCI0_MEM_SIZE _128M 479#define CONFIG_SYS_PCI1_MEM_BASE 0x88000000 480#define CONFIG_SYS_PCI1_MEM_SIZE _128M 481 482#define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE) 483#define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE) 484 485/* PCI I/O MAP section */ 486#define CONFIG_SYS_PCI0_IO_BASE 0xfa000000 487#define CONFIG_SYS_PCI0_IO_SIZE _16M 488#define CONFIG_SYS_PCI1_IO_BASE 0xfb000000 489#define CONFIG_SYS_PCI1_IO_SIZE _16M 490 491#define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE) 492#define CONFIG_SYS_PCI0_IO_SPACE_PCI (CONFIG_SYS_PCI0_IO_BASE) /* ronen we want phy=bus 0x00000000 */ 493#define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE) 494#define CONFIG_SYS_PCI1_IO_SPACE_PCI (CONFIG_SYS_PCI1_IO_BASE) /* ronen we want phy=bus 0x00000000 */ 495 496#if defined (CONFIG_750CX) 497#define CONFIG_SYS_PCI_IDSEL 0x0 498#else 499#define CONFIG_SYS_PCI_IDSEL 0x30 500#endif 501/*---------------------------------------------------------------------- 502 * Initial BAT mappings 503 */ 504 505/* NOTES: 506 * 1) GUARDED and WRITE_THRU not allowed in IBATS 507 * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT 508 */ 509 510/* SDRAM */ 511#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 512#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 513#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 514#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 515 516/* init ram */ 517#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 518#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP) 519#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 520#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 521 522/* PCI0, PCI1 in one BAT */ 523#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS 524#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 525#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) 526#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 527 528/* GT regs, bootrom, all the devices, PCI I/O */ 529#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) 530#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) 531#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) 532#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 533 534/* I2C addresses for the two DIMM SPD chips */ 535#define DIMM0_I2C_ADDR 0x56 536#define DIMM1_I2C_ADDR 0x54 537 538/* 539 * For booting Linux, the board info and command line data 540 * have to be in the first 8 MB of memory, since this is 541 * the maximum mapped by the Linux kernel during initialization. 542 */ 543#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ 544 545/*----------------------------------------------------------------------- 546 * FLASH organization 547 */ 548#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 549#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ 550 551#define CONFIG_SYS_EXTRA_FLASH_DEVICE DEVICE3 /* extra flash at device 3 */ 552#define CONFIG_SYS_EXTRA_FLASH_WIDTH 4 /* 32 bit */ 553#define CONFIG_SYS_BOOT_FLASH_WIDTH 1 /* 8 bit */ 554 555#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 556#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 557#define CONFIG_SYS_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */ 558#define CONFIG_SYS_FLASH_CFI 1 559 560#define CONFIG_ENV_IS_IN_FLASH 1 561#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ 562#define CONFIG_ENV_SECT_SIZE 0x10000 563#define CONFIG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */ 564/* #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) */ 565 566/*----------------------------------------------------------------------- 567 * Cache Configuration 568 */ 569#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ 570#if defined(CONFIG_CMD_KGDB) 571#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 572#endif 573 574/*----------------------------------------------------------------------- 575 * L2CR setup -- make sure this is right for your board! 576 * look in include/mpc74xx.h for the defines used here 577 */ 578 579#define CONFIG_SYS_L2 580 581 582#if defined (CONFIG_750CX) || defined (CONFIG_750FX) 583#define L2_INIT 0 584#else 585 586#define L2_INIT 0 587/* 588#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ 589 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) 590*/ 591#endif 592 593#define L2_ENABLE (L2_INIT | L2CR_L2E) 594 595#define CONFIG_SYS_BOARD_ASM_INIT 1 596 597#endif /* __CONFIG_H */ 598