1/* 2 * Copyright (C) 2004 Arabella Software Ltd. 3 * Yuli Barcohen <yuli@arabellasw.com> 4 * 5 * Support for Interphase iSPAN Communications Controllers 6 * (453x and others). Tested on 4532. 7 * 8 * Derived from iSPAN 4539 port (iphase4539) by 9 * Wolfgang Grandegger <wg@denx.de> 10 * 11 * See file CREDITS for list of people who contributed to this 12 * project. 13 * 14 * This program is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License as 16 * published by the Free Software Foundation; either version 2 of 17 * the License, or (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program; if not, write to the Free Software 26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 27 * MA 02111-1307 USA 28 */ 29#ifndef __CONFIG_H 30#define __CONFIG_H 31 32#define CONFIG_MPC8260 /* This is an MPC8260 CPU */ 33#define CONFIG_ISPAN /* ...on one of Interphase iSPAN boards */ 34#define CONFIG_CPM2 1 /* Has a CPM2 */ 35 36#define CONFIG_SYS_TEXT_BASE 0xFE7A0000 37 38/*----------------------------------------------------------------------- 39 * Select serial console configuration 40 * 41 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then 42 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 43 * for SCC). 44 * 45 * If CONFIG_CONS_NONE is defined, then the serial console routines must be 46 * defined elsewhere (for example, on the cogent platform, there are serial 47 * ports on the motherboard which are used for the serial console - see 48 * cogent/cma101/serial.[ch]). 49 */ 50#define CONFIG_CONS_ON_SMC /* Define if console on SMC */ 51#undef CONFIG_CONS_ON_SCC /* Define if console on SCC */ 52#undef CONFIG_CONS_NONE /* Define if console on something else */ 53#define CONFIG_CONS_INDEX 1 /* Which serial channel for console */ 54 55/*----------------------------------------------------------------------- 56 * Select Ethernet configuration 57 * 58 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then 59 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 60 * for FCC). 61 * 62 * If CONFIG_ETHER_NONE is defined, then either the Ethernet routines must 63 * be defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. 64 */ 65#undef CONFIG_ETHER_ON_SCC /* Define if Ethernet on SCC */ 66#define CONFIG_ETHER_ON_FCC /* Define if Ethernet on FCC */ 67#undef CONFIG_ETHER_NONE /* Define if Ethernet on something else */ 68#define CONFIG_ETHER_INDEX 3 /* Which channel for Ethernrt */ 69 70#ifdef CONFIG_ETHER_ON_FCC 71 72#if CONFIG_ETHER_INDEX == 3 73 74#define CONFIG_SYS_PHY_ADDR 0 75#define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16) 76#define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK) 77 78#endif /* CONFIG_ETHER_INDEX == 3 */ 79 80#define CONFIG_SYS_CPMFCR_RAMTYPE 0 81#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) 82 83#define CONFIG_MII /* MII PHY management */ 84#define CONFIG_BITBANGMII /* Bit-bang MII PHY management */ 85/* 86 * GPIO pins used for bit-banged MII communications 87 */ 88#define MDIO_PORT 3 /* Port D */ 89#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ 90 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) 91#define MDC_DECLARE MDIO_DECLARE 92 93 94#define CONFIG_SYS_MDIO_PIN 0x00040000 /* PD13 */ 95#define CONFIG_SYS_MDC_PIN 0x00080000 /* PD12 */ 96 97#define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN) 98#define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN) 99#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0) 100 101#define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \ 102 else iop->pdat &= ~CONFIG_SYS_MDIO_PIN 103 104#define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \ 105 else iop->pdat &= ~CONFIG_SYS_MDC_PIN 106 107#define MIIDELAY udelay(1) 108 109#endif /* CONFIG_ETHER_ON_FCC */ 110 111#define CONFIG_8260_CLKIN 65536000 /* in Hz */ 112#define CONFIG_BAUDRATE 38400 113 114 115/* 116 * BOOTP options 117 */ 118#define CONFIG_BOOTP_BOOTFILESIZE 119#define CONFIG_BOOTP_BOOTPATH 120#define CONFIG_BOOTP_GATEWAY 121#define CONFIG_BOOTP_HOSTNAME 122 123 124/* 125 * Command line configuration. 126 */ 127#include <config_cmd_default.h> 128 129#define CONFIG_CMD_ASKENV 130#define CONFIG_CMD_DHCP 131#define CONFIG_CMD_IMMAP 132#define CONFIG_CMD_MII 133#define CONFIG_CMD_PING 134#define CONFIG_CMD_REGINFO 135 136 137#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 138#define CONFIG_BOOTCOMMAND "bootm fe010000" /* autoboot command */ 139#define CONFIG_BOOTARGS "root=/dev/ram rw" 140 141#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */ 142#undef CONFIG_WATCHDOG /* Disable platform specific watchdog */ 143 144/*----------------------------------------------------------------------- 145 * Miscellaneous configurable options 146 */ 147#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 148#define CONFIG_SYS_HUSH_PARSER 149#define CONFIG_SYS_LONGHELP /* #undef to save memory */ 150#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 151#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ 152#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */ 153#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 154 155#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ 156#define CONFIG_SYS_MEMTEST_END 0x03B00000 /* 1 ... 59 MB in SDRAM */ 157 158#define CONFIG_SYS_LOAD_ADDR 0x100000 /* Default load address */ 159 160#define CONFIG_SYS_HZ 1000 /* Decrementer freq: 1 ms ticks */ 161 162#define CONFIG_SYS_RESET_ADDRESS 0x09900000 163 164#define CONFIG_MISC_INIT_R /* We need misc_init_r() */ 165 166/*----------------------------------------------------------------------- 167 * For booting Linux, the board info and command line data 168 * have to be in the first 8 MB of memory, since this is 169 * the maximum mapped by the Linux kernel during initialization. 170 */ 171#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 172 173#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 174#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ 175#ifdef CONFIG_BZIP2 176#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */ 177#else 178#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */ 179#endif /* CONFIG_BZIP2 */ 180 181/*----------------------------------------------------------------------- 182 * FLASH organization 183 */ 184#define CONFIG_SYS_FLASH_BASE 0xFE000000 185#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ 186#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ 187#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max num of memory banks */ 188#define CONFIG_SYS_MAX_FLASH_SECT 142 /* Max num of sects on one chip */ 189 190/* Environment is in flash, there is little space left in Serial EEPROM */ 191#define CONFIG_ENV_IS_IN_FLASH 192#define CONFIG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */ 193#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 194#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 195#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 196#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 197 198/*----------------------------------------------------------------------- 199 * Hard Reset Configuration Words 200 * 201 * If you change bits in the HRCW, you must also change the CONFIG_SYS_* 202 * defines for the various registers affected by the HRCW e.g. changing 203 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. 204 */ 205/* 0x1686B245 */ 206#define CONFIG_SYS_HRCW_MASTER (HRCW_EBM | HRCW_BPS01 | HRCW_CIP |\ 207 HRCW_L2CPC10 | HRCW_ISB110 |\ 208 HRCW_BMS | HRCW_MMR11 | HRCW_APPC10 |\ 209 HRCW_CS10PC01 | HRCW_MODCK_H0101 \ 210 ) 211/* No slaves */ 212#define CONFIG_SYS_HRCW_SLAVE1 0 213#define CONFIG_SYS_HRCW_SLAVE2 0 214#define CONFIG_SYS_HRCW_SLAVE3 0 215#define CONFIG_SYS_HRCW_SLAVE4 0 216#define CONFIG_SYS_HRCW_SLAVE5 0 217#define CONFIG_SYS_HRCW_SLAVE6 0 218#define CONFIG_SYS_HRCW_SLAVE7 0 219 220/*----------------------------------------------------------------------- 221 * Internal Memory Mapped Register 222 */ 223#define CONFIG_SYS_IMMR 0xF0F00000 224#ifdef CONFIG_SYS_REV_B 225#define CONFIG_SYS_DEFAULT_IMMR 0xFF000000 226#endif /* CONFIG_SYS_REV_B */ 227/*----------------------------------------------------------------------- 228 * Definitions for initial stack pointer and data area (in DPRAM) 229 */ 230#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 231#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ 232#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 233#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 234 235/*----------------------------------------------------------------------- 236 * Cache Configuration 237 */ 238#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ 239 240/*----------------------------------------------------------------------- 241 * HIDx - Hardware Implementation-dependent Registers 2-11 242 *----------------------------------------------------------------------- 243 * HID0 also contains cache control. 244 * 245 * HID1 has only read-only information - nothing to set. 246 */ 247#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ 248 HID0_IFEM|HID0_ABE) 249#define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE) 250#define CONFIG_SYS_HID2 0 251 252/*----------------------------------------------------------------------- 253 * RMR - Reset Mode Register 5-5 254 *----------------------------------------------------------------------- 255 * turn on Checkstop Reset Enable 256 */ 257#define CONFIG_SYS_RMR RMR_CSRE 258 259/*----------------------------------------------------------------------- 260 * BCR - Bus Configuration 4-25 261 *----------------------------------------------------------------------- 262 */ 263#define CONFIG_SYS_BCR 0xA01C0000 264 265/*----------------------------------------------------------------------- 266 * SIUMCR - SIU Module Configuration 4-31 267 *----------------------------------------------------------------------- 268 */ 269#define CONFIG_SYS_SIUMCR 0x42250000/* 0x4205C000 */ 270 271/*----------------------------------------------------------------------- 272 * SYPCR - System Protection Control 4-35 273 * SYPCR can only be written once after reset! 274 *----------------------------------------------------------------------- 275 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable 276 */ 277#if defined (CONFIG_WATCHDOG) 278#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ 279 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) 280#else 281#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ 282 SYPCR_SWRI|SYPCR_SWP) 283#endif /* CONFIG_WATCHDOG */ 284 285/*----------------------------------------------------------------------- 286 * TMCNTSC - Time Counter Status and Control 4-40 287 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, 288 * and enable Time Counter 289 *----------------------------------------------------------------------- 290 */ 291#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) 292 293/*----------------------------------------------------------------------- 294 * PISCR - Periodic Interrupt Status and Control 4-42 295 *----------------------------------------------------------------------- 296 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable 297 * Periodic timer 298 */ 299#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) 300 301/*----------------------------------------------------------------------- 302 * SCCR - System Clock Control 9-8 303 *----------------------------------------------------------------------- 304 * Ensure DFBRG is Divide by 16 305 */ 306#define CONFIG_SYS_SCCR SCCR_DFBRG01 307 308/*----------------------------------------------------------------------- 309 * RCCR - RISC Controller Configuration 13-7 310 *----------------------------------------------------------------------- 311 */ 312#define CONFIG_SYS_RCCR 0 313 314/*----------------------------------------------------------------------- 315 * Init Memory Controller: 316 * 317 * Bank Bus Machine PortSize Device 318 * ---- --- ------- ----------------------------- ------ 319 * 0 60x GPCM 8 bit (Rev.B)/16 bit (Rev.D) Flash 320 * 1 60x SDRAM 64 bit SDRAM 321 * 2 Local SDRAM 32 bit SDRAM 322 */ 323#define CONFIG_SYS_USE_FIRMWARE /* If defined - do not initialise memory 324 controller, rely on initialisation 325 performed by the Interphase boot firmware. 326 */ 327 328#define CONFIG_SYS_OR0_PRELIM 0xFE000882 329#ifdef CONFIG_SYS_REV_B 330#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BRx_PS_8 | BRx_V) 331#else /* Rev. D */ 332#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BRx_PS_16 | BRx_V) 333#endif /* CONFIG_SYS_REV_B */ 334 335#define CONFIG_SYS_MPTPR 0x7F00 336 337/* Please note that 60x SDRAM MUST start at 0 */ 338#define CONFIG_SYS_SDRAM_BASE 0x00000000 339#define CONFIG_SYS_60x_BR 0x00000041 340#define CONFIG_SYS_60x_OR 0xF0002CD0 341#define CONFIG_SYS_PSDMR 0x0049929A 342#define CONFIG_SYS_PSRT 0x07 343 344#define CONFIG_SYS_LSDRAM_BASE 0xF7000000 345#define CONFIG_SYS_LOC_BR 0x00001861 346#define CONFIG_SYS_LOC_OR 0xFF803280 347#define CONFIG_SYS_LSDMR 0x8285A552 348#define CONFIG_SYS_LSRT 0x07 349 350#endif /* __CONFIG_H */ 351