1/* 2 * (C) Copyright 2000-2010 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* 25 * Pantelis Antoniou, Intracom S.A., panto@intracom.gr 26 * U-Boot port on NetVia board 27 */ 28 29#ifndef __CONFIG_H 30#define __CONFIG_H 31 32/* 33 * High Level Configuration Options 34 * (easy to change) 35 */ 36 37#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ 38#define CONFIG_NETVIA 1 /* ...on a NetVia board */ 39 40#define CONFIG_SYS_TEXT_BASE 0x40000000 41 42#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1 43#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 44#undef CONFIG_8xx_CONS_SMC2 45#undef CONFIG_8xx_CONS_NONE 46#else 47#define CONFIG_8xx_CONS_NONE 48#define CONFIG_MAX3100_SERIAL 49#endif 50 51#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ 52 53#define CONFIG_XIN 10000000 54#define CONFIG_8xx_GCLK_FREQ 80000000 55 56#if 0 57#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ 58#else 59#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 60#endif 61 62#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */ 63 64#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" 65 66#undef CONFIG_BOOTARGS 67#define CONFIG_BOOTCOMMAND \ 68 "tftpboot; " \ 69 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ 70 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ 71 "bootm" 72 73#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ 74#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 75 76#undef CONFIG_WATCHDOG /* watchdog disabled */ 77 78#define CONFIG_STATUS_LED 1 /* Status LED enabled */ 79 80#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 81#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ 82#endif 83 84#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 85 86/* 87 * BOOTP options 88 */ 89#define CONFIG_BOOTP_SUBNETMASK 90#define CONFIG_BOOTP_GATEWAY 91#define CONFIG_BOOTP_HOSTNAME 92#define CONFIG_BOOTP_BOOTPATH 93#define CONFIG_BOOTP_BOOTFILESIZE 94#define CONFIG_BOOTP_NISDOMAIN 95 96 97#undef CONFIG_MAC_PARTITION 98#undef CONFIG_DOS_PARTITION 99 100#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 101 102 103/* 104 * Command line configuration. 105 */ 106#include <config_cmd_default.h> 107 108#define CONFIG_CMD_DHCP 109#define CONFIG_CMD_PING 110 111#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 112/* #define CONFIG_CMD_NAND */ /* disabled */ 113#endif 114 115 116#define CONFIG_BOARD_EARLY_INIT_F 1 117#define CONFIG_MISC_INIT_R 118 119/* 120 * Miscellaneous configurable options 121 */ 122#define CONFIG_SYS_LONGHELP /* undef to save memory */ 123#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 124#if defined(CONFIG_CMD_KGDB) 125#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 126#else 127#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 128#endif 129#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 130#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 131#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 132 133#define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */ 134#define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */ 135 136#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 137 138#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 139 140/* 141 * Low Level Configuration Settings 142 * (address mappings, register initial values, etc.) 143 * You should know what you are doing if you make changes here. 144 */ 145/*----------------------------------------------------------------------- 146 * Internal Memory Mapped Register 147 */ 148#define CONFIG_SYS_IMMR 0xFF000000 149 150/*----------------------------------------------------------------------- 151 * Definitions for initial stack pointer and data area (in DPRAM) 152 */ 153#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 154#define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */ 155#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 156#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 157 158/*----------------------------------------------------------------------- 159 * Start addresses for the final memory configuration 160 * (Set up by the startup code) 161 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 162 */ 163#define CONFIG_SYS_SDRAM_BASE 0x00000000 164#define CONFIG_SYS_FLASH_BASE 0x40000000 165#if defined(DEBUG) 166#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 167#else 168#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ 169#endif 170#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 171#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 172 173/* 174 * For booting Linux, the board info and command line data 175 * have to be in the first 8 MB of memory, since this is 176 * the maximum mapped by the Linux kernel during initialization. 177 */ 178#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 179 180/*----------------------------------------------------------------------- 181 * FLASH organization 182 */ 183#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 184#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ 185 186#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 187#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 188 189#define CONFIG_ENV_IS_IN_FLASH 1 190#define CONFIG_ENV_SECT_SIZE 0x10000 191 192#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000) 193#define CONFIG_ENV_SIZE 0x4000 194 195#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x70000) 196#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 197 198/*----------------------------------------------------------------------- 199 * Cache Configuration 200 */ 201#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 202#if defined(CONFIG_CMD_KGDB) 203#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 204#endif 205 206/*----------------------------------------------------------------------- 207 * SYPCR - System Protection Control 11-9 208 * SYPCR can only be written once after reset! 209 *----------------------------------------------------------------------- 210 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 211 */ 212#if defined(CONFIG_WATCHDOG) 213#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 214 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 215#else 216#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 217#endif 218 219/*----------------------------------------------------------------------- 220 * SIUMCR - SIU Module Configuration 11-6 221 *----------------------------------------------------------------------- 222 * PCMCIA config., multi-function pin tri-state 223 */ 224#ifndef CONFIG_CAN_DRIVER 225#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) 226#else /* we must activate GPL5 in the SIUMCR for CAN */ 227#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) 228#endif /* CONFIG_CAN_DRIVER */ 229 230/*----------------------------------------------------------------------- 231 * TBSCR - Time Base Status and Control 11-26 232 *----------------------------------------------------------------------- 233 * Clear Reference Interrupt Status, Timebase freezing enabled 234 */ 235#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 236 237/*----------------------------------------------------------------------- 238 * RTCSC - Real-Time Clock Status and Control Register 11-27 239 *----------------------------------------------------------------------- 240 */ 241#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 242 243/*----------------------------------------------------------------------- 244 * PISCR - Periodic Interrupt Status and Control 11-31 245 *----------------------------------------------------------------------- 246 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 247 */ 248#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 249 250/*----------------------------------------------------------------------- 251 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 252 *----------------------------------------------------------------------- 253 * Reset PLL lock status sticky bit, timer expired status bit and timer 254 * interrupt status bit 255 * 256 * 257 *----------------------------------------------------------------------- 258 * SCCR - System Clock and reset Control Register 15-27 259 *----------------------------------------------------------------------- 260 * Set clock output, timebase and RTC source and divider, 261 * power management and some other internal clocks 262 */ 263 264#define SCCR_MASK SCCR_EBDF11 265 266#if CONFIG_8xx_GCLK_FREQ == 50000000 267 268#define CONFIG_SYS_PLPRCR ( ((5 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 269#define CONFIG_SYS_SCCR (SCCR_TBS | \ 270 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 271 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 272 SCCR_DFALCD00) 273 274#elif CONFIG_8xx_GCLK_FREQ == 80000000 275 276#define CONFIG_SYS_PLPRCR ( ((8 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 277#define CONFIG_SYS_SCCR (SCCR_TBS | \ 278 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 279 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 280 SCCR_DFALCD00 | SCCR_EBDF01) 281 282#endif 283 284/*----------------------------------------------------------------------- 285 * 286 *----------------------------------------------------------------------- 287 * 288 */ 289/*#define CONFIG_SYS_DER 0x2002000F*/ 290#define CONFIG_SYS_DER 0 291 292/* 293 * Init Memory Controller: 294 * 295 * BR0/1 and OR0/1 (FLASH) 296 */ 297 298#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 299 300/* used to re-map FLASH both when starting from SRAM or FLASH: 301 * restrict access enough to keep SRAM working (if any) 302 * but not too much to meddle with FLASH accesses 303 */ 304#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 305#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 306 307/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ 308#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX) 309 310#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 311#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 312#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) 313 314/* 315 * BR3 and OR3 (SDRAM) 316 * 317 */ 318#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */ 319#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ 320 321/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 322#define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS) 323 324#define CONFIG_SYS_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM) 325#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V) 326 327/* 328 * Memory Periodic Timer Prescaler 329 */ 330 331/* periodic timer for refresh */ 332#define CONFIG_SYS_MAMR_PTA 208 333 334/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 335#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 336 337/* 338 * MAMR settings for SDRAM 339 */ 340 341/* 9 column SDRAM */ 342#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 343 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 344 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 345 346/* Ethernet at SCC2 */ 347#define CONFIG_SCC2_ENET 348 349/****************************************************************/ 350 351#define DSP_SIZE 0x00010000 /* 64K */ 352#define FPGA_SIZE 0x00010000 /* 64K */ 353 354#define DSP0_BASE 0xF1000000 355#define DSP1_BASE (DSP0_BASE + DSP_SIZE) 356#define FPGA_BASE (DSP1_BASE + DSP_SIZE) 357 358#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 359 360#define ER_SIZE 0x00010000 /* 64K */ 361#define ER_BASE (FPGA_BASE + FPGA_SIZE) 362 363#define NAND_SIZE 0x00010000 /* 64K */ 364#define NAND_BASE (ER_BASE + ER_SIZE) 365 366#endif 367 368/****************************************************************/ 369 370#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 371 372#define STATUS_LED_BIT 0x00000001 /* bit 31 */ 373#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) 374#define STATUS_LED_STATE STATUS_LED_BLINKING 375 376#define STATUS_LED_BIT1 0x00000002 /* bit 30 */ 377#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) 378#define STATUS_LED_STATE1 STATUS_LED_OFF 379 380#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ 381#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ 382 383#endif 384 385 386/*****************************************************************************/ 387 388#ifndef __ASSEMBLY__ 389 390#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 391 392/* LEDs */ 393 394/* last value written to the external register; we cannot read back */ 395extern unsigned int last_er_val; 396 397/* led_id_t is unsigned long mask */ 398typedef unsigned int led_id_t; 399 400static inline void __led_init(led_id_t mask, int state) 401{ 402 unsigned int new_er_val; 403 404 if (state) 405 new_er_val = last_er_val & ~mask; 406 else 407 new_er_val = last_er_val | mask; 408 409 *(volatile unsigned int *)ER_BASE = new_er_val; 410 last_er_val = new_er_val; 411} 412 413static inline void __led_toggle(led_id_t mask) 414{ 415 unsigned int new_er_val; 416 417 new_er_val = last_er_val ^ mask; 418 *(volatile unsigned int *)ER_BASE = new_er_val; 419 last_er_val = new_er_val; 420} 421 422static inline void __led_set(led_id_t mask, int state) 423{ 424 unsigned int new_er_val; 425 426 if (state) 427 new_er_val = last_er_val & ~mask; 428 else 429 new_er_val = last_er_val | mask; 430 431 *(volatile unsigned int *)ER_BASE = new_er_val; 432 last_er_val = new_er_val; 433} 434 435/* MAX3100 console */ 436#define MAX3100_SPI_RXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) 437#define MAX3100_SPI_RXD_BIT 0x00000008 438 439#define MAX3100_SPI_TXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) 440#define MAX3100_SPI_TXD_BIT 0x00000004 441 442#define MAX3100_SPI_CLK_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) 443#define MAX3100_SPI_CLK_BIT 0x00000002 444 445#define MAX3100_CS_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) 446#define MAX3100_CS_BIT 0x0010 447 448#endif 449 450#endif 451 452/*************************************************************************************************/ 453 454#endif /* __CONFIG_H */ 455