1/* 2 * (C) Copyright 2003 3 * MuLogic B.V. 4 * 5 * (C) Copyright 2002 6 * Simple Network Magic Corporation 7 * 8 * (C) Copyright 2000 9 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 10 * 11 * See file CREDITS for list of people who contributed to this 12 * project. 13 * 14 * This program is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License as 16 * published by the Free Software Foundation; either version 2 of 17 * the License, or (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program; if not, write to the Free Software 26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 27 * MA 02111-1307 USA 28 */ 29 30/* 31 * board/config.h - configuration options, board specific 32 */ 33 34#ifndef __CONFIG_H 35#define __CONFIG_H 36 37/* various debug settings */ 38#undef CONFIG_SYS_DEVICE_NULLDEV /* null device */ 39#undef CONFIG_SILENT_CONSOLE /* silent console */ 40#undef CONFIG_SYS_CONSOLE_INFO_QUIET /* silent console ? */ 41#undef DEBUG_FLASH /* debug flash code */ 42#undef FLASH_DEBUG /* debug fash code */ 43#undef DEBUG_ENV /* debug environment code */ 44 45#define CONFIG_SYS_DIRECT_FLASH_TFTP 1 /* allow direct tftp to flash */ 46#define CONFIG_ENV_OVERWRITE 1 /* allow overwrite MAC address */ 47 48/* 49 * High Level Configuration Options 50 * (easy to change) 51 */ 52#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ 53#define CONFIG_QS850 1 /* ...on a QS850 module */ 54#define CONFIG_SCC2_ENET 1 /* SCC2 10BaseT ethernet */ 55 56#define CONFIG_SYS_TEXT_BASE 0xFFF00000 57 58/* Select the target clock speed */ 59#undef CONFIG_CLOCK_16MHZ /* cpu=16,777,216 Hz, mem=16Mhz */ 60#undef CONFIG_CLOCK_33MHZ /* cpu=33,554,432 Hz, mem=33Mhz */ 61#undef CONFIG_CLOCK_50MHZ /* cpu=49,971,200 Hz, mem=33Mhz */ 62#define CONFIG_CLOCK_66MHZ 1 /* cpu=67,108,864 Hz, mem=66Mhz */ 63#undef CONFIG_CLOCK_80MHZ /* cpu=79,986,688 Hz, mem=33Mhz */ 64 65#ifdef CONFIG_CLOCK_16MHZ 66#define CONFIG_CLOCK_MULT 512 67#endif 68 69#ifdef CONFIG_CLOCK_33MHZ 70#define CONFIG_CLOCK_MULT 1024 71#endif 72 73#ifdef CONFIG_CLOCK_50MHZ 74#define CONFIG_CLOCK_MULT 1525 75#endif 76 77#ifdef CONFIG_CLOCK_66MHZ 78#define CONFIG_CLOCK_MULT 2048 79#endif 80 81#ifdef CONFIG_CLOCK_80MHZ 82#define CONFIG_CLOCK_MULT 2441 83#endif 84 85/* choose flash size, 4Mb or 8Mb */ 86#define CONFIG_FLASH_4MB 1 /* board has 4Mb flash */ 87#undef CONFIG_FLASH_8MB /* board has 8Mb flash */ 88 89#define CONFIG_CLOCK_BASE 32768 /* Base clock input freq */ 90 91#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 92#undef CONFIG_8xx_CONS_SMC2 93#undef CONFIG_8xx_CONS_NONE 94 95#define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */ 96 97#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in MHz */ 98 99/* Define default IP addresses */ 100#define CONFIG_IPADDR 192.168.1.99 /* own ip address */ 101#define CONFIG_SERVERIP 192.168.1.19 /* used for tftp (not nfs?) */ 102 103/* message to say directly after booting */ 104#define CONFIG_PREBOOT "echo '';" \ 105 "echo 'type:';" \ 106 "echo 'run boot_nfs to boot to NFS';" \ 107 "echo 'run boot_flash to boot to flash';" \ 108 "echo '';" \ 109 "echo 'run flash_rootfs to install a new rootfs';" \ 110 "echo 'run flash_env to clear the env sector';" \ 111 "echo 'run flash_rw to clear the rw fs';" \ 112 "echo 'run flash_uboot to install a new u-boot';" \ 113 "echo 'run flash_kernel to install a new kernel';" 114 115/* wait 5 seconds before executing CONFIG_BOOTCOMMAND */ 116#define CONFIG_BOOTDELAY 5 117#define CONFIG_BOOTCOMMAND "run boot_nfs" 118 119#undef CONFIG_BOOTARGS /* made by set_nfs of set_flash */ 120 121/* Our flash filesystem looks like this 122 * 123 * 4Mb board: 124 * ffc0 0000 - ffeb ffff root filesystem (jffs2) (~3Mb) 125 * ffec 0000 - ffed ffff read-write filesystem (ext2) 126 * ffee 0000 - ffef ffff environment 127 * fff0 0000 - fff1 ffff u-boot 128 * fff2 0000 - ffff ffff linux kernel 129 * 130 * 8Mb board: 131 * ff80 0000 - ffeb ffff root filesystem (jffs2) (~7Mb) 132 * ffec 0000 - ffed ffff read-write filesystem (ext2) 133 * ffee 0000 - ffef ffff environment 134 * fff0 0000 - fff1 ffff u-boot 135 * fff2 0000 - ffff ffff linux kernel 136 * 137 */ 138 139/* environment for 4Mb board */ 140#ifdef CONFIG_FLASH_4MB 141#define CONFIG_EXTRA_ENV_SETTINGS \ 142 "serial#=QS850\0" \ 143 "hostname=qs850\0" \ 144 "netdev=eth0\0" \ 145 "ethaddr=00:01:02:B4:36:56\0" \ 146 "rootpath=/exports/rootfs\0" \ 147 "mtdparts=mtdparts=phys:2816k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \ 148 /* fill in variables */ \ 149 "set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \ 150 "set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \ 151 "set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \ 152 /* commands */ \ 153 "boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \ 154 "boot_flash=run set_ip; run set_flash; bootm fff20000\0" \ 155 /* reinstall flash parts */ \ 156 "flash_rootfs=protect off ffc00000 ffebffff; era ffc00000 ffebffff; tftp ffc00000 /tftpboot/rootfs.jffs2\0" \ 157 "flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \ 158 "flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \ 159 "flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.4mb.bin\0" \ 160 "flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0" 161#endif /* CONFIG_FLASH_4MB */ 162 163/* environment for 8Mb board */ 164#ifdef CONFIG_FLASH_8MB 165#define CONFIG_EXTRA_ENV_SETTINGS \ 166 "serial#=QS850\0" \ 167 "hostname=qs850\0" \ 168 "netdev=eth0\0" \ 169 "ethaddr=00:01:02:B4:36:56\0" \ 170 "rootpath=/exports/rootfs\0" \ 171 "mtdparts=mtdparts=phys:6912k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \ 172 /* fill in variables */ \ 173 "set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \ 174 "set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \ 175 "set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \ 176 /* commands */ \ 177 "boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \ 178 "boot_flash=run set_ip; run set_flash; bootm fff20000\0" \ 179 /* reinstall flash parts */ \ 180 "flash_rootfs=protect off ff800000 ffebffff; era ff800000 ffebffff; tftp ff800000 /tftpboot/rootfs.jffs2\0" \ 181 "flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \ 182 "flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \ 183 "flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.8mb.bin\0" \ 184 "flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0" 185#endif /* CONFIG_FLASH_8MB */ 186 187#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 188#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 189#undef CONFIG_WATCHDOG /* watchdog disabled */ 190#undef CONFIG_STATUS_LED /* Status LED disabled */ 191#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 192 193/* 194 * BOOTP options 195 */ 196#define CONFIG_BOOTP_SUBNETMASK 197#define CONFIG_BOOTP_GATEWAY 198#define CONFIG_BOOTP_HOSTNAME 199#define CONFIG_BOOTP_BOOTPATH 200#define CONFIG_BOOTP_BOOTFILESIZE 201 202#undef CONFIG_MAC_PARTITION 203#undef CONFIG_DOS_PARTITION 204 205#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 206 207 208/* 209 * Command line configuration. 210 */ 211 212#define CONFIG_CMD_BDI 213#define CONFIG_CMD_BOOTD 214#define CONFIG_CMD_CONSOLE 215#define CONFIG_CMD_DATE 216#define CONFIG_CMD_SAVEENV 217#define CONFIG_CMD_FLASH 218#define CONFIG_CMD_IMI 219#define CONFIG_CMD_IMMAP 220#define CONFIG_CMD_MEMORY 221#define CONFIG_CMD_NET 222#define CONFIG_CMD_RUN 223 224 225/*----------------------------------------------------------------------- 226 * Environment variable storage is in FLASH, one sector before U-boot 227 */ 228#define CONFIG_ENV_IS_IN_FLASH 1 229#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128Kb, one whole sector */ 230#define CONFIG_ENV_SIZE 0x2000 /* 8kb */ 231#define CONFIG_ENV_ADDR 0xffee0000 /* address of env sector */ 232 233/*----------------------------------------------------------------------- 234 * Miscellaneous configurable options 235 */ 236#define CONFIG_SYS_LONGHELP /* undef to save memory */ 237#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 238 239#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ 240 241#if defined(CONFIG_CMD_KGDB) 242#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 243#else 244#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 245#endif 246#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 247#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 248#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 249 250#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works */ 251#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 252 253#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ 254 255#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 256 257/*----------------------------------------------------------------------- 258 * Low Level Configuration Settings 259 * (address mappings, register initial values, etc.) 260 * You should know what you are doing if you make changes here. 261 */ 262 263/*----------------------------------------------------------------------- 264 * Internal Memory Mapped Register 265 */ 266#define CONFIG_SYS_IMMR 0xFF000000 267 268/*----------------------------------------------------------------------- 269 * Definitions for initial stack pointer and data area (in DPRAM) 270 */ 271#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 272#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ 273#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 274#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 275 276/*----------------------------------------------------------------------- 277 * Start addresses for the final memory configuration 278 * (Set up by the startup code) 279 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 280 */ 281#define CONFIG_SYS_SDRAM_BASE 0x00000000 282#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* Allow an 8Mbyte window */ 283 284#define FLASH_BASE0_4M_PRELIM 0xFFC00000 /* Base for 4M Flash */ 285#define FLASH_BASE0_8M_PRELIM 0xFF800000 /* Base for 8M Flash */ 286 287#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ 288#define CONFIG_SYS_MONITOR_BASE 0xFFF00000 /* U-boot location */ 289#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 290 291/* 292 * For booting Linux, the board info and command line data 293 * have to be in the first 8 MB of memory, since this is 294 * the maximum mapped by the Linux kernel during initialization. 295 */ 296#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 297 298/*----------------------------------------------------------------------- 299 * TODO flash parameters 300 * FLASH organization for Intel Strataflash 301 */ 302#undef CONFIG_SYS_FLASH_16BIT /* 32-bit wide flash memory */ 303#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 304#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ 305 306#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 307#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 308 309/*----------------------------------------------------------------------- 310 * Cache Configuration 311 */ 312#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 313#if defined(CONFIG_CMD_KGDB) 314#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 315#endif 316 317/*----------------------------------------------------------------------- 318 * SYPCR - System Protection Control 11-9 319 * SYPCR can only be written once after reset! 320 *----------------------------------------------------------------------- 321 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 322 */ 323 324#ifdef CONFIG_WATCHDOG 325#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP) 326#else 327#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWRI | SYPCR_SWP) 328#endif 329 330/*----------------------------------------------------------------------- 331 * SIUMCR - SIU Module Configuration 11-6 332 *----------------------------------------------------------------------- 333 */ 334#define CONFIG_SYS_SIUMCR (SIUMCR_DLK | SIUMCR_DPC | SIUMCR_MPRE | SIUMCR_MLRC01 | SIUMCR_GB5E) 335 336/*----------------------------------------------------------------------- 337 * TBSCR - Time Base Status and Control 11-26 338 *----------------------------------------------------------------------- 339 */ 340#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 341 342/*----------------------------------------------------------------------- 343 * RTCSC - Real-Time Clock Status and Control Register 11-27 344 *----------------------------------------------------------------------- 345 */ 346#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 347 348/*----------------------------------------------------------------------- 349 * PISCR - Periodic Interrupt Status and Control 11-31 350 *----------------------------------------------------------------------- 351 */ 352#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 353 354/*----------------------------------------------------------------------- 355 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 356 *----------------------------------------------------------------------- 357 */ 358 359/* MF (Multiplication Factor of SPLL) */ 360/* Sets the QS850 to specified clock from 32KHz clock at EXTAL. */ 361#define vPLPRCR_MF ((CONFIG_CLOCK_MULT+1) << 20) 362#define CONFIG_SYS_PLPRCR (vPLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | PLPRCR_LOLRE) 363 364/*----------------------------------------------------------------------- 365 * SCCR - System Clock and reset Control Register 15-27 366 *----------------------------------------------------------------------- 367 */ 368#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ) 369#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG00) 370#define CONFIG_SYS_BRGCLK_PRESCALE 1 371#endif 372 373#if defined(CONFIG_CLOCK_66MHZ) 374#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG01) 375#define CONFIG_SYS_BRGCLK_PRESCALE 4 376#endif 377 378#if defined(CONFIG_CLOCK_80MHZ) 379#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_EBDF01 | SCCR_DFBRG01) 380#define CONFIG_SYS_BRGCLK_PRESCALE 4 381#endif 382 383#define SCCR_MASK CONFIG_SYS_SCCR 384 385/*----------------------------------------------------------------------- 386 * Debug Enable Register 387 * 0x73E67C0F - All interrupts handled by BDM 388 * 0x00824001 - Only interrupts needed by MWDebug.exe handled by BDM 389 *----------------------------------------------------------------------- 390#define CONFIG_SYS_DER 0x73E67C0F 391#define CONFIG_SYS_DER 0x0082400F 392 393 #------------------------------------------------------------------------- 394 # Program the Debug Enable Register (DER). This register provides the user 395 # with the reason for entering into the debug mode. We want all conditions 396 # to end up as an exception. We don't want to enter into debug mode for 397 # any condition. See the back of of the Development Support section of the 398 # MPC860 User Manual for a description of this register. 399 #------------------------------------------------------------------------- 400*/ 401#define CONFIG_SYS_DER 0 402 403/*----------------------------------------------------------------------- 404 * Memory Controller Initialization Constants 405 *----------------------------------------------------------------------- 406 */ 407 408/* 409 * BR0 and OR0 (AMD dual FLASH devices) 410 * Base address = 0xFFF0_0000 - 0xFFF7_FFFF (After relocation) 411 */ 412#define CONFIG_SYS_PRELIM_OR_AM 413#define CONFIG_SYS_OR_TIMING_FLASH 414 415/* 416 *----------------------------------------------------------------------- 417 * Base Register 0 (BR0): Bank 0 is assigned to the 8Mbyte (2M X 32) 418 * flash that resides on the QS850. 419 *----------------------------------------------------------------------- 420 */ 421 422/* BA (Base Address) = 0xFF80+0b for a total of 17 bits. 17 bit base addr */ 423/* represents a minumum 32K block size. */ 424#define vBR0_BA ((0xFF80 << 16) + (0 << 15)) 425#define CONFIG_SYS_BR0_PRELIM (vBR0_BA | BR_V) 426 427/* AM (Address Mask) = 0xFF80+0b = We've masked the upper 9 bits */ 428/* which defines a 8 Mbyte memory block. */ 429#define vOR0_AM ((0xFF80 << 16) + (0 << 15)) 430 431#if defined(CONFIG_CLOCK_50MHZ) || defined(CONFIG_CLOCK_80MHZ) 432/* 0101 = Add a 5 clock cycle wait state */ 433#define CONFIG_SYS_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | 0R_ACS_DIV4 | OR_BI | OR_SCY_5_CLK) 434#endif 435 436#if defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_66MHZ) 437/* 0011 = Add a 3 clock cycle wait state */ 438/* 29.8ns clock * (3 + 2) = 149ns cycle time */ 439#define CONFIG_SYS_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK) 440#endif 441 442#if defined(CONFIG_CLOCK_16MHZ) 443/* 0010 = Add a 2 clock cycle wait state */ 444#define CONFIG_SYS_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK) 445#endif 446 447/* 448 * BR1 and OR1 (SDRAM) 449 * Base Address = 0x00000000 - 0x00FF_FFFF (16M After relocation) 450 * Base Address = 0x00000000 - 0x01FF_FFFF (32M After relocation) 451 * Base Address = 0x00000000 - 0x03FF_FFFF (64M After relocation) 452 * Base Address = 0x00000000 - 0x07FF_FFFF (128M After relocation) 453 */ 454 455#define SDRAM_BASE 0x00000000 /* SDRAM bank */ 456#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ 457 458/* AM (Address Mask) = 0xF800+0b = We've masked the upper 5 bits which 459 * represents a 128 Mbyte block the DRAM in 460 * this address base. 461 */ 462#define vOR1_AM ((0xF800 << 16) + (0 << 15)) 463#define vBR1_BA ((0x0000 << 16) + (0 << 15)) 464#define CONFIG_SYS_OR1 (vOR1_AM | OR_CSNT_SAM | OR_BI) 465#define CONFIG_SYS_BR1 (vBR1_BA | BR_MS_UPMA | BR_V) 466 467/* Machine A Mode Register */ 468 469/* PTA Periodic Timer A */ 470 471#if defined(CONFIG_CLOCK_80MHZ) 472#define vMAMR_PTA (19 << 24) 473#endif 474 475#if defined(CONFIG_CLOCK_66MHZ) 476#define vMAMR_PTA (16 << 24) 477#endif 478 479#if defined(CONFIG_CLOCK_50MHZ) 480#define vMAMR_PTA (195 << 24) 481#endif 482 483#if defined(CONFIG_CLOCK_33MHZ) 484#define vMAMR_PTA (131 << 24) 485#endif 486 487#if defined(CONFIG_CLOCK_16MHZ) 488#define vMAMR_PTA (65 << 24) 489#endif 490 491/* For boards with 16M of SDRAM */ 492#define SDRAM_16M_MAX_SIZE 0x01000000 /* max 16MB SDRAM */ 493#define CONFIG_SYS_16M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\ 494MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 495 496/* For boards with 32M of SDRAM */ 497#define SDRAM_32M_MAX_SIZE 0x02000000 /* max 32MB SDRAM */ 498#define CONFIG_SYS_32M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\ 499MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 500 501 502/* Memory Periodic Timer Prescaler Register */ 503 504#if defined(CONFIG_CLOCK_66MHZ) || defined(CONFIG_CLOCK_80MHZ) 505/* Divide by 32 */ 506#define CONFIG_SYS_MPTPR 0x02 507#endif 508 509#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ) 510/* Divide by 16 */ 511#define CONFIG_SYS_MPTPR 0x04 512#endif 513 514/* 515 * BR2 and OR2 (Unused) 516 * Base address = 0xF020_0000 - 0xF020_0FFF 517 * 518 */ 519#define CONFIG_SYS_OR2_PRELIM 0xFFF00000 520#define CONFIG_SYS_BR2_PRELIM 0xF0200000 521 522/* 523 * BR3 and OR3 (External Bus CS3) 524 * Base address = 0xF030_0000 - 0xF030_0FFF 525 * 526 */ 527#define CONFIG_SYS_OR3_PRELIM 0xFFF00000 528#define CONFIG_SYS_BR3_PRELIM 0xF0300000 529 530/* 531 * BR4 and OR4 (External Bus CS3) 532 * Base address = 0xF040_0000 - 0xF040_0FFF 533 * 534 */ 535#define CONFIG_SYS_OR4_PRELIM 0xFFF00000 536#define CONFIG_SYS_BR4_PRELIM 0xF0400000 537 538 539/* 540 * BR4 and OR4 (External Bus CS3) 541 * Base address = 0xF050_0000 - 0xF050_0FFF 542 * 543 */ 544#define CONFIG_SYS_OR5_PRELIM 0xFFF00000 545#define CONFIG_SYS_BR5_PRELIM 0xF0500000 546 547/* 548 * BR6 and OR6 (Unused) 549 * Base address = 0xF060_0000 - 0xF060_0FFF 550 * 551 */ 552#define CONFIG_SYS_OR6_PRELIM 0xFFF00000 553#define CONFIG_SYS_BR6_PRELIM 0xF0600000 554 555/* 556 * BR7 and OR7 (Unused) 557 * Base address = 0xF070_0000 - 0xF070_0FFF 558 * 559 */ 560#define CONFIG_SYS_OR7_PRELIM 0xFFF00000 561#define CONFIG_SYS_BR7_PRELIM 0xF0700000 562 563/* 564 * Sanity checks 565 */ 566#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET) 567#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured 568#endif 569 570#endif /* __CONFIG_H */ 571