1/* 2 * (C) Copyright 2000 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* 25 * board/config.h - configuration options, board specific 26 */ 27 28#ifndef __CONFIG_H 29#define __CONFIG_H 30 31/* 32 * High Level Configuration Options 33 * (easy to change) 34 */ 35 36#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ 37#define CONFIG_SPD823TS 1 /* ...on a SPD823TS board */ 38 39#define CONFIG_SYS_TEXT_BASE 0xFF000000 40 41#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ 42 43#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 44#undef CONFIG_8xx_CONS_SMC2 45#undef CONFIG_8xx_CONS_NONE 46#define CONFIG_BAUDRATE 115200 47#if 0 48#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ 49#else 50#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 51#endif 52 53#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ 54 55#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ 56 57#define CONFIG_BOOTARGS "root=/dev/nfs rw " \ 58 "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \ 59 "nfsaddrs=10.0.0.99:10.0.0.2" 60 61#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 62#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 63 64#undef CONFIG_WATCHDOG /* watchdog disabled */ 65 66 67/* 68 * Command line configuration. 69 */ 70#include <config_cmd_default.h> 71 72#define CONFIG_CMD_IDE 73 74#undef CONFIG_CMD_SAVEENV 75#undef CONFIG_CMD_FLASH 76 77 78#define CONFIG_MAC_PARTITION 79#define CONFIG_DOS_PARTITION 80 81/* 82 * BOOTP options 83 */ 84#define CONFIG_BOOTP_SUBNETMASK 85#define CONFIG_BOOTP_GATEWAY 86#define CONFIG_BOOTP_HOSTNAME 87#define CONFIG_BOOTP_BOOTPATH 88#define CONFIG_BOOTP_BOOTFILESIZE 89 90 91/*----------------------------------------------------------------------*/ 92#define CONFIG_ETHADDR 00:D0:93:00:01:CB 93#define CONFIG_IPADDR 10.0.0.98 94#define CONFIG_SERVERIP 10.0.0.1 95#undef CONFIG_BOOTCOMMAND 96#define CONFIG_BOOTCOMMAND "tftp 200000 uImage;bootm 200000" 97/*----------------------------------------------------------------------*/ 98 99/* 100 * Miscellaneous configurable options 101 */ 102#define CONFIG_SYS_LONGHELP /* undef to save memory */ 103#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 104#if defined(CONFIG_CMD_KGDB) 105#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 106#else 107#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 108#endif 109#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 110#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 111#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 112 113#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ 114#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ 115 116#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ 117 118#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ 119 120#define CONFIG_SYS_PC_IDE_RESET ((ushort)0x0008) /* PC 12 */ 121 122#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 123 124/* 125 * Low Level Configuration Settings 126 * (address mappings, register initial values, etc.) 127 * You should know what you are doing if you make changes here. 128 */ 129/*----------------------------------------------------------------------- 130 * Internal Memory Mapped Register 131 */ 132#define CONFIG_SYS_IMMR 0xFFF00000 /* was: 0xFF000000 */ 133 134/*----------------------------------------------------------------------- 135 * Definitions for initial stack pointer and data area (in DPRAM) 136 */ 137#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 138#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ 139#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 140#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 141 142/*----------------------------------------------------------------------- 143 * Start addresses for the final memory configuration 144 * (Set up by the startup code) 145 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 146 */ 147#define CONFIG_SYS_SDRAM_BASE 0x00000000 148#define CONFIG_SYS_FLASH_BASE 0xFF000000 149#ifdef DEBUG 150#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ 151#else 152#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 153#endif 154#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 155#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 156 157/* 158 * For booting Linux, the board info and command line data 159 * have to be in the first 8 MB of memory, since this is 160 * the maximum mapped by the Linux kernel during initialization. 161 */ 162#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 163/*----------------------------------------------------------------------- 164 * FLASH organization 165 */ 166#define CONFIG_SYS_MAX_FLASH_BANKS 0 /* max number of memory banks */ 167#define CONFIG_SYS_MAX_FLASH_SECT 0 /* max number of sectors on one chip */ 168 169#define CONFIG_SYS_FLASH_ERASE_TOUT 0 /* Timeout for Flash Erase (in ms) */ 170#define CONFIG_SYS_FLASH_WRITE_TOUT 0 /* Timeout for Flash Write (in ms) */ 171 172#define CONFIG_ENV_IS_IN_FLASH 1 173#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ 174#define CONFIG_ENV_SIZE 0x0800 /* Total Size of Environment Sector */ 175/*----------------------------------------------------------------------- 176 * Cache Configuration 177 */ 178#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 179#if defined(CONFIG_CMD_KGDB) 180#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 181#endif 182 183/*----------------------------------------------------------------------- 184 * SYPCR - System Protection Control 11-9 185 * SYPCR can only be written once after reset! 186 *----------------------------------------------------------------------- 187 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 188 */ 189#if defined(CONFIG_WATCHDOG) 190#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 191 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 192#else 193#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 194#endif 195 196/*----------------------------------------------------------------------- 197 * SIUMCR - SIU Module Configuration 11-6 198 *----------------------------------------------------------------------- 199 * PCMCIA config., multi-function pin tri-state 200 */ 201/* 0x00000040 */ 202#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00 | SIUMCR_GB5E) 203 204/*----------------------------------------------------------------------- 205 * TBSCR - Time Base Status and Control 11-26 206 *----------------------------------------------------------------------- 207 * Clear Reference Interrupt Status, Timebase freezing enabled 208 */ 209#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 210 211/*----------------------------------------------------------------------- 212 * PISCR - Periodic Interrupt Status and Control 11-31 213 *----------------------------------------------------------------------- 214 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 215 */ 216#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 217 218/*----------------------------------------------------------------------- 219 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 220 *----------------------------------------------------------------------- 221 * Reset PLL lock status sticky bit, timer expired status bit and timer 222 * interrupt status bit, set PLL multiplication factor ! 223 */ 224/* 0x00b0c0c0 */ 225#define CONFIG_SYS_PLPRCR \ 226 ( (11 << PLPRCR_MF_SHIFT) | \ 227 PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/ \ 228 /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \ 229 PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \ 230 ) 231 232/*----------------------------------------------------------------------- 233 * SCCR - System Clock and reset Control Register 15-27 234 *----------------------------------------------------------------------- 235 * Set clock output, timebase and RTC source and divider, 236 * power management and some other internal clocks 237 */ 238#define SCCR_MASK SCCR_EBDF11 239/* 0x01800014 */ 240#define CONFIG_SYS_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \ 241 SCCR_RTDIV | SCCR_RTSEL | \ 242 /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ 243 SCCR_EBDF00 | SCCR_DFSYNC00 | \ 244 SCCR_DFBRG00 | SCCR_DFNL000 | \ 245 SCCR_DFNH000 | SCCR_DFLCD101 | \ 246 SCCR_DFALCD00) 247 248/*----------------------------------------------------------------------- 249 * RTCSC - Real-Time Clock Status and Control Register 250 *----------------------------------------------------------------------- 251 */ 252/* 0x00C3 */ 253#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 254 255 256/*----------------------------------------------------------------------- 257 * RCCR - RISC Controller Configuration Register 258 *----------------------------------------------------------------------- 259 */ 260/* TIMEP=2 */ 261#define CONFIG_SYS_RCCR 0x0200 262 263/*----------------------------------------------------------------------- 264 * RMDS - RISC Microcode Development Support Control Register 265 *----------------------------------------------------------------------- 266 */ 267#define CONFIG_SYS_RMDS 0 268 269/*----------------------------------------------------------------------- 270 * SDSR - SDMA Status Register 271 *----------------------------------------------------------------------- 272 */ 273#define CONFIG_SYS_SDSR ((u_char)0x83) 274 275/*----------------------------------------------------------------------- 276 * SDMR - SDMA Mask Register 277 *----------------------------------------------------------------------- 278 */ 279#define CONFIG_SYS_SDMR ((u_char)0x00) 280 281/*----------------------------------------------------------------------- 282 * 283 * Interrupt Levels 284 *----------------------------------------------------------------------- 285 */ 286#define CONFIG_SYS_CPM_INTERRUPT 13 /* SIU_LEVEL6 */ 287 288/*----------------------------------------------------------------------- 289 * PCMCIA stuff 290 *----------------------------------------------------------------------- 291 * 292 */ 293#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 294#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 295#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 296#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 297#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 298#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 299#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 300#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 301 302/*----------------------------------------------------------------------- 303 * IDE/ATA stuff 304 *----------------------------------------------------------------------- 305 */ 306#define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */ 307#define CONFIG_IDE_LED 1 /* LED for ide supported */ 308#define CONFIG_IDE_RESET 1 /* reset for ide supported */ 309 310#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */ 311#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ 312 313#define CONFIG_SYS_ATA_BASE_ADDR 0xFE100000 314#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 315#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0C00 316 317#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ 318#define CONFIG_SYS_ATA_REG_OFFSET 0x0080 /* Offset for normal register accesses */ 319#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 /* Offset for alternate registers */ 320 321/*----------------------------------------------------------------------- 322 * 323 *----------------------------------------------------------------------- 324 * 325 */ 326#define CONFIG_SYS_DER 0 327 328/* 329 * Init Memory Controller: 330 * 331 * BR0/1 and OR0/1 (FLASH) 332 */ 333 334#define FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank #0 */ 335#define FLASH_BASE1_PRELIM 0xFF080000 /* FLASH bank #1 */ 336 337/* used to re-map FLASH both when starting from SRAM or FLASH: 338 * restrict access enough to keep SRAM working (if any) 339 * but not too much to meddle with FLASH accesses 340 */ 341/* EPROMs are 512kb */ 342#define CONFIG_SYS_REMAP_OR_AM 0xFFF80000 /* OR addr mask */ 343#define CONFIG_SYS_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */ 344 345/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ 346#define CONFIG_SYS_OR_TIMING_FLASH (/* OR_CSNT_SAM | */ OR_ACS_DIV4 | OR_BI | \ 347 OR_SCY_5_CLK | OR_EHTR) 348 349#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 350#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 351/* 16 bit, bank valid */ 352#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) 353 354#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 355#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 356/* 16 bit, bank valid */ 357#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) 358 359/* 360 * BR2-5 and OR2-5 (SRAM/SDRAM/PER8/SHARC) 361 * 362 */ 363#define SRAM_BASE 0xFE200000 /* SRAM bank */ 364#define SRAM_OR_AM 0xFFE00000 /* SRAM is 2 MB */ 365 366#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */ 367#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ 368#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */ 369 370#define PER8_BASE 0xFE000000 /* PER8 bank */ 371#define PER8_OR_AM 0xFFF00000 /* PER8 is 1 MB */ 372 373#define SHARC_BASE 0xFE400000 /* SHARC bank */ 374#define SHARC_OR_AM 0xFFC00000 /* SHARC is 4 MB */ 375 376/* SRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 377 378#define CONFIG_SYS_OR_TIMING_SRAM 0x00000D42 /* SRAM-Timing */ 379#define CONFIG_SYS_OR2 (SRAM_OR_AM | CONFIG_SYS_OR_TIMING_SRAM ) 380#define CONFIG_SYS_BR2 ((SRAM_BASE & BR_BA_MSK) | BR_PS_16 | BR_V ) 381 382/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 383 384#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 /* SDRAM-Timing */ 385#define CONFIG_SYS_OR3_PRELIM (SDRAM_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 386#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V ) 387 388#define CONFIG_SYS_OR_TIMING_PER8 0x00000F32 /* PER8-Timing */ 389#define CONFIG_SYS_OR4 (PER8_OR_AM | CONFIG_SYS_OR_TIMING_PER8 ) 390#define CONFIG_SYS_BR4 ((PER8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) 391 392#define CONFIG_SYS_OR_TIMING_SHARC 0x00000700 /* SHARC-Timing */ 393#define CONFIG_SYS_OR5 (SHARC_OR_AM | CONFIG_SYS_OR_TIMING_SHARC ) 394#define CONFIG_SYS_BR5 ((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V ) 395/* 396 * Memory Periodic Timer Prescaler 397 */ 398 399/* periodic timer for refresh */ 400#define CONFIG_SYS_MBMR_PTB 204 401 402/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ 403#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 404#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 405 406/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 407#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 408#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 409 410/* 411 * MBMR settings for SDRAM 412 */ 413 414/* 8 column SDRAM */ 415#define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \ 416 MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \ 417 MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) 418 419#endif /* __CONFIG_H */ 420