1/* 2 * (C) Copyright 2001-2005 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* ------------------------------------------------------------------------- */ 25 26/* 27 * board/config.h - configuration options, board specific 28 */ 29 30#ifndef __CONFIG_H 31#define __CONFIG_H 32 33/* 34 * High Level Configuration Options 35 * (easy to change) 36 */ 37 38#define CONFIG_MPC824X 1 39#define CONFIG_MPC8240 1 40#define CONFIG_SANDPOINT 1 41 42#define CONFIG_SYS_TEXT_BASE 0xFFF00000 43#define CONFIG_SYS_LDSCRIPT "board/sandpoint/u-boot.lds" 44 45#if 0 46#define USE_DINK32 1 47#else 48#undef USE_DINK32 49#endif 50 51#define CONFIG_CONS_INDEX 1 52#define CONFIG_BAUDRATE 9600 53 54#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 55 56#define CONFIG_TIMESTAMP /* Print image info with timestamp */ 57 58#define CONFIG_PREBOOT "echo;" \ 59 "echo Type \"run net_nfs\" to mount root filesystem over NFS;" \ 60 "echo" 61 62#undef CONFIG_BOOTARGS 63 64#define CONFIG_EXTRA_ENV_SETTINGS \ 65 "netdev=eth0\0" \ 66 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 67 "nfsroot=${serverip}:${rootpath}\0" \ 68 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 69 "addip=setenv bootargs ${bootargs} " \ 70 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 71 ":${hostname}:${netdev}:off panic=1\0" \ 72 "net_self=tftp ${kernel_addr} ${bootfile};" \ 73 "tftp ${ramdisk_addr} ${ramdisk};" \ 74 "run ramargs addip;" \ 75 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 76 "net_nfs=tftp ${kernel_addr} ${bootfile};" \ 77 "run nfsargs addip;bootm\0" \ 78 "rootpath=/opt/eldk/ppc_82xx\0" \ 79 "bootfile=/tftpboot/SP8240/uImage\0" \ 80 "ramdisk=/tftpboot/SP8240/uRamdisk\0" \ 81 "kernel_addr=200000\0" \ 82 "ramdisk_addr=400000\0" \ 83 "" 84#define CONFIG_BOOTCOMMAND "run flash_self" 85 86 87/* 88 * BOOTP options 89 */ 90#define CONFIG_BOOTP_BOOTFILESIZE 91#define CONFIG_BOOTP_BOOTPATH 92#define CONFIG_BOOTP_GATEWAY 93#define CONFIG_BOOTP_HOSTNAME 94 95 96/* 97 * Command line configuration. 98 */ 99#include <config_cmd_default.h> 100 101#define CONFIG_CMD_DHCP 102#define CONFIG_CMD_ELF 103#define CONFIG_CMD_I2C 104#define CONFIG_CMD_SDRAM 105#define CONFIG_CMD_EEPROM 106#define CONFIG_CMD_NFS 107#define CONFIG_CMD_PCI 108#define CONFIG_CMD_SNTP 109 110 111#define CONFIG_DRAM_SPEED 100 /* MHz */ 112 113/* 114 * Miscellaneous configurable options 115 */ 116#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */ 117#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 118#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 119#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 120#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 121#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 122#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ 123#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 124 125/*----------------------------------------------------------------------- 126 * PCI stuff 127 *----------------------------------------------------------------------- 128 */ 129#define CONFIG_PCI /* include pci support */ 130#undef CONFIG_PCI_PNP 131 132 133#define CONFIG_EEPRO100 134#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ 135 136#define PCI_ENET0_IOADDR 0x80000000 137#define PCI_ENET0_MEMADDR 0x80000000 138#define PCI_ENET1_IOADDR 0x81000000 139#define PCI_ENET1_MEMADDR 0x81000000 140 141 142/*----------------------------------------------------------------------- 143 * Start addresses for the final memory configuration 144 * (Set up by the startup code) 145 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 146 */ 147#define CONFIG_SYS_SDRAM_BASE 0x00000000 148#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 149 150#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 151 152#if defined (USE_DINK32) 153#define CONFIG_SYS_MONITOR_LEN 0x00030000 154#define CONFIG_SYS_MONITOR_BASE 0x00090000 155#define CONFIG_SYS_RAMBOOT 1 156#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 157#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 158#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 159#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 160#else 161#undef CONFIG_SYS_RAMBOOT 162#define CONFIG_SYS_MONITOR_LEN 0x00030000 163#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 164 165 166#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 167#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 168#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 169 170#endif 171 172#define CONFIG_SYS_FLASH_BASE 0xFFF00000 173#if 0 174#define CONFIG_SYS_FLASH_SIZE (512 * 1024) /* sandpoint has tiny eeprom */ 175#else 176#define CONFIG_SYS_FLASH_SIZE (1024 * 1024) /* Unity has onboard 1MByte flash */ 177#endif 178#define CONFIG_ENV_IS_IN_FLASH 1 179#define CONFIG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */ 180#define CONFIG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */ 181 182#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ 183 184#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ 185#define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */ 186 187#define CONFIG_SYS_EUMB_ADDR 0xFC000000 188 189#define CONFIG_SYS_ISA_MEM 0xFD000000 190#define CONFIG_SYS_ISA_IO 0xFE000000 191 192#define CONFIG_SYS_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */ 193#define CONFIG_SYS_FLASH_RANGE_SIZE 0x01000000 194#define FLASH_BASE0_PRELIM 0xFFF00000 /* sandpoint flash */ 195#define FLASH_BASE1_PRELIM 0xFF000000 /* PMC onboard flash */ 196 197/* 198 * select i2c support configuration 199 * 200 * Supported configurations are {none, software, hardware} drivers. 201 * If the software driver is chosen, there are some additional 202 * configuration items that the driver uses to drive the port pins. 203 */ 204#define CONFIG_HARD_I2C 1 /* To enable I2C support */ 205#undef CONFIG_SOFT_I2C /* I2C bit-banged */ 206#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 207#define CONFIG_SYS_I2C_SLAVE 0x7F 208 209#ifdef CONFIG_SOFT_I2C 210#error "Soft I2C is not configured properly. Please review!" 211#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ 212#define I2C_ACTIVE (iop->pdir |= 0x00010000) 213#define I2C_TRISTATE (iop->pdir &= ~0x00010000) 214#define I2C_READ ((iop->pdat & 0x00010000) != 0) 215#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ 216 else iop->pdat &= ~0x00010000 217#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ 218 else iop->pdat &= ~0x00020000 219#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ 220#endif /* CONFIG_SOFT_I2C */ 221 222 223#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */ 224#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ 225#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* write page size */ 226#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */ 227 228 229#define CONFIG_SYS_FLASH_BANKS { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM } 230 231/*----------------------------------------------------------------------- 232 * Definitions for initial stack pointer and data area (in DPRAM) 233 */ 234 235 236/* #define CONFIG_WINBOND_83C553 1 / *has a winbond bridge */ 237#define CONFIG_SYS_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */ 238#define CONFIG_SYS_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */ 239#define CONFIG_SYS_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */ 240 241#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */ 242#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ 243 244/* 245 * NS87308 Configuration 246 */ 247#define CONFIG_NS87308 /* Nat Semi super-io controller on ISA bus */ 248 249#define CONFIG_SYS_NS87308_BADDR_10 1 250 251#define CONFIG_SYS_NS87308_DEVS ( CONFIG_SYS_NS87308_UART1 | \ 252 CONFIG_SYS_NS87308_UART2 | \ 253 CONFIG_SYS_NS87308_POWRMAN | \ 254 CONFIG_SYS_NS87308_RTC_APC ) 255 256#undef CONFIG_SYS_NS87308_PS2MOD 257 258#define CONFIG_SYS_NS87308_CS0_BASE 0x0076 259#define CONFIG_SYS_NS87308_CS0_CONF 0x30 260#define CONFIG_SYS_NS87308_CS1_BASE 0x0075 261#define CONFIG_SYS_NS87308_CS1_CONF 0x30 262#define CONFIG_SYS_NS87308_CS2_BASE 0x0074 263#define CONFIG_SYS_NS87308_CS2_CONF 0x30 264 265/* 266 * NS16550 Configuration 267 */ 268#define CONFIG_SYS_NS16550 269#define CONFIG_SYS_NS16550_SERIAL 270 271#define CONFIG_SYS_NS16550_REG_SIZE 1 272 273#define CONFIG_SYS_NS16550_CLK 1843200 274 275#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART1_BASE) 276#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART2_BASE) 277 278/* 279 * Low Level Configuration Settings 280 * (address mappings, register initial values, etc.) 281 * You should know what you are doing if you make changes here. 282 */ 283 284#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ 285#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 1 286 287#define CONFIG_SYS_ROMNAL 7 /*rom/flash next access time */ 288#define CONFIG_SYS_ROMFAL 11 /*rom/flash access time */ 289 290#define CONFIG_SYS_REFINT 430 /* no of clock cycles between CBR refresh cycles */ 291 292/* the following are for SDRAM only*/ 293#define CONFIG_SYS_BSTOPRE 121 /* Burst To Precharge, sets open page interval */ 294#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */ 295#define CONFIG_SYS_RDLAT 4 /* data latency from read command */ 296#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */ 297#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */ 298#define CONFIG_SYS_ACTORW 3 /* Activate to R/W */ 299#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ 300#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */ 301#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */ 302 303#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 304 305/* memory bank settings*/ 306/* 307 * only bits 20-29 are actually used from these vales to set the 308 * start/end address the upper two bits will be 0, and the lower 20 309 * bits will be set to 0x00000 for a start address, or 0xfffff for an 310 * end address 311 */ 312#define CONFIG_SYS_BANK0_START 0x00000000 313#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) 314#define CONFIG_SYS_BANK0_ENABLE 1 315#define CONFIG_SYS_BANK1_START 0x3ff00000 316#define CONFIG_SYS_BANK1_END 0x3fffffff 317#define CONFIG_SYS_BANK1_ENABLE 0 318#define CONFIG_SYS_BANK2_START 0x3ff00000 319#define CONFIG_SYS_BANK2_END 0x3fffffff 320#define CONFIG_SYS_BANK2_ENABLE 0 321#define CONFIG_SYS_BANK3_START 0x3ff00000 322#define CONFIG_SYS_BANK3_END 0x3fffffff 323#define CONFIG_SYS_BANK3_ENABLE 0 324#define CONFIG_SYS_BANK4_START 0x00000000 325#define CONFIG_SYS_BANK4_END 0x00000000 326#define CONFIG_SYS_BANK4_ENABLE 0 327#define CONFIG_SYS_BANK5_START 0x00000000 328#define CONFIG_SYS_BANK5_END 0x00000000 329#define CONFIG_SYS_BANK5_ENABLE 0 330#define CONFIG_SYS_BANK6_START 0x00000000 331#define CONFIG_SYS_BANK6_END 0x00000000 332#define CONFIG_SYS_BANK6_ENABLE 0 333#define CONFIG_SYS_BANK7_START 0x00000000 334#define CONFIG_SYS_BANK7_END 0x00000000 335#define CONFIG_SYS_BANK7_ENABLE 0 336/* 337 * Memory bank enable bitmask, specifying which of the banks defined above 338 are actually present. MSB is for bank #7, LSB is for bank #0. 339 */ 340#define CONFIG_SYS_BANK_ENABLE 0x01 341 342#define CONFIG_SYS_ODCR 0xff /* configures line driver impedances, */ 343 /* see 8240 book for bit definitions */ 344#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */ 345 /* currently accessed page in memory */ 346 /* see 8240 book for details */ 347 348/* SDRAM 0 - 256MB */ 349#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 350#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 351 352/* stack in DCACHE @ 1GB (no backing mem) */ 353#if defined(USE_DINK32) 354#define CONFIG_SYS_IBAT1L (0x40000000 | BATL_PP_00 ) 355#define CONFIG_SYS_IBAT1U (0x40000000 | BATU_BL_128K ) 356#else 357#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) 358#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 359#endif 360 361/* PCI memory */ 362#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) 363#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) 364 365/* Flash, config addrs, etc */ 366#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) 367#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 368 369#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 370#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 371#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 372#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 373#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 374#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 375#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 376#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 377 378/* 379 * For booting Linux, the board info and command line data 380 * have to be in the first 8 MB of memory, since this is 381 * the maximum mapped by the Linux kernel during initialization. 382 */ 383#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 384/*----------------------------------------------------------------------- 385 * FLASH organization 386 */ 387#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 388#define CONFIG_SYS_MAX_FLASH_SECT 20 /* max number of sectors on one chip */ 389 390#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 391#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 392 393/*----------------------------------------------------------------------- 394 * Cache Configuration 395 */ 396#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */ 397#if defined(CONFIG_CMD_KGDB) 398# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 399#endif 400 401/* values according to the manual */ 402 403#define CONFIG_DRAM_50MHZ 1 404#define CONFIG_SDRAM_50MHZ 405 406#undef NR_8259_INTS 407#define NR_8259_INTS 1 408 409 410#define CONFIG_DISK_SPINUP_TIME 1000000 411 412 413#endif /* __CONFIG_H */ 414