LXR uboot/include/configs/TQM8272.h

   1/*
   2 * (C) Copyright 2006
   3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24/*
  25 * board/config.h - configuration options, board specific
  26 */
  27
  28#ifndef __CONFIG_H
  29#define __CONFIG_H
  30
  31/*
  32 * High Level Configuration Options
  33 * (easy to change)
  34 */
  35
  36#define CONFIG_MPC8260          1       /* This is a MPC8260 CPU                */
  37#define CONFIG_MPC8272_FAMILY   1
  38#define CONFIG_TQM8272          1
  39
  40#define CONFIG_SYS_TEXT_BASE    0x40000000
  41
  42#define CONFIG_GET_CPU_STR_F    1       /* Get the CPU ID STR */
  43#define CONFIG_BOARD_GET_CPU_CLK_F      1 /* Get the CLKIN from board fct */
  44
  45#define STK82xx_150             1       /* on a STK82xx.150 */
  46
  47#define CONFIG_CPM2             1       /* Has a CPM2 */
  48
  49#define CONFIG_82xx_CONS_SMC1   1       /* console on SMC1              */
  50
  51#define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  52
  53#define CONFIG_BOARD_EARLY_INIT_R       1
  54
  55#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
  56#define CONFIG_BAUDRATE         230400
  57#else
  58#define CONFIG_BAUDRATE         115200
  59#endif
  60
  61#define CONFIG_PREBOOT  "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
  62
  63#undef  CONFIG_BOOTARGS
  64
  65#define CONFIG_EXTRA_ENV_SETTINGS                                       \
  66        "netdev=eth0\0"                                                 \
  67        "consdev=ttyCPM0\0"                                             \
  68        "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  69                "nfsroot=${serverip}:${rootpath}\0"                     \
  70        "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  71        "hostname=tqm8272\0"                                            \
  72        "addip=setenv bootargs ${bootargs} "                            \
  73                "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  74                ":${hostname}:${netdev}:off panic=1\0"                  \
  75        "addcons=setenv bootargs ${bootargs} "                          \
  76                "console=$(consdev),$(baudrate)\0"                      \
  77        "flash_nfs=run nfsargs addip addcons;"                          \
  78                "bootm ${kernel_addr}\0"                                \
  79        "flash_self=run ramargs addip addcons;"                         \
  80                "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
  81        "net_nfs=tftp 300000 ${bootfile};"                              \
  82                "run nfsargs addip addcons;bootm\0"                     \
  83        "rootpath=/opt/eldk/ppc_82xx\0"                                 \
  84        "bootfile=/tftpboot/tqm8272/uImage\0"                           \
  85        "kernel_addr=40080000\0"                                        \
  86        "ramdisk_addr=40100000\0"                                       \
  87        "load=tftp 300000 /tftpboot/tqm8272/u-boot.bin\0"               \
  88        "update=protect off 40000000 4003ffff;era 40000000 4003ffff;"   \
  89                "cp.b 300000 40000000 40000;"                           \
  90                "setenv filesize;saveenv\0"                             \
  91        "cphwib=cp.b 4003fc00 33fc00 400\0"                             \
  92        "upd=run load cphwib update\0"                                  \
  93        ""
  94#define CONFIG_BOOTCOMMAND      "run flash_self"
  95
  96#define CONFIG_I2C      1
  97
  98#if CONFIG_I2C
  99/* enable I2C and select the hardware/software driver */
 100#undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
 101#define CONFIG_SOFT_I2C         1       /* I2C bit-banged               */
 102#define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address  */
 103#define CONFIG_SYS_I2C_SLAVE            0x7F
 104
 105/*
 106 * Software (bit-bang) I2C driver configuration
 107 */
 108#define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
 109#define I2C_ACTIVE      (iop->pdir |=  0x00010000)
 110#define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
 111#define I2C_READ        ((iop->pdat & 0x00010000) != 0)
 112#define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00010000; \
 113                        else    iop->pdat &= ~0x00010000
 114#define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00020000; \
 115                        else    iop->pdat &= ~0x00020000
 116#define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 117
 118#define CONFIG_I2C_X
 119
 120/* EEPROM */
 121#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 122#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 123#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* and takes up to 10 msec */
 124#define CONFIG_SYS_I2C_MULTI_EEPROMS            1       /* more than one eeprom */
 125
 126/* I2C RTC */
 127#define CONFIG_RTC_DS1337               /* Use ds1337 rtc via i2c       */
 128#define CONFIG_SYS_I2C_RTC_ADDR 0x68    /* at address 0x68              */
 129
 130/* I2C SYSMON (LM75) */
 131#define CONFIG_DTT_LM75         1               /* ON Semi's LM75       */
 132#define CONFIG_DTT_SENSORS      {0}             /* Sensor addresses     */
 133#define CONFIG_SYS_DTT_MAX_TEMP 70
 134#define CONFIG_SYS_DTT_LOW_TEMP -30
 135#define CONFIG_SYS_DTT_HYSTERESIS       3
 136
 137#else
 138#undef CONFIG_HARD_I2C
 139#undef CONFIG_SOFT_I2C
 140#endif
 141
 142/*
 143 * select serial console configuration
 144 *
 145 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 146 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 147 * for SCC).
 148 *
 149 * if CONFIG_CONS_NONE is defined, then the serial console routines must
 150 * defined elsewhere (for example, on the cogent platform, there are serial
 151 * ports on the motherboard which are used for the serial console - see
 152 * cogent/cma101/serial.[ch]).
 153 */
 154#define CONFIG_CONS_ON_SMC              /* define if console on SMC */
 155#undef  CONFIG_CONS_ON_SCC              /* define if console on SCC */
 156#undef  CONFIG_CONS_NONE                /* define if console on something else*/
 157#ifdef CONFIG_82xx_CONS_SMC1
 158#define CONFIG_CONS_INDEX       1       /* which serial channel for console */
 159#endif
 160#ifdef CONFIG_82xx_CONS_SMC2
 161#define CONFIG_CONS_INDEX       2       /* which serial channel for console */
 162#endif
 163
 164#undef  CONFIG_CONS_USE_EXTC            /* SMC/SCC use ext clock not brg_clk */
 165#define CONFIG_CONS_EXTC_RATE   3686400 /* SMC/SCC ext clk rate in Hz */
 166#define CONFIG_CONS_EXTC_PINSEL 0       /* pin select 0=CLK3/CLK9 */
 167
 168/*
 169 * select ethernet configuration
 170 *
 171 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 172 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 173 * for FCC)
 174 *
 175 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 176 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
 177 *
 178 * (On TQM8272 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
 179 * X.29 connector, and FCC2 is hardwired to the X.1 connector)
 180 */
 181#define CONFIG_SYS_FCC_ETHERNET
 182
 183#if defined(CONFIG_SYS_FCC_ETHERNET)
 184#undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC       */
 185#define CONFIG_ETHER_ON_FCC             /* define if ether on FCC       */
 186#undef  CONFIG_ETHER_NONE               /* define if ether on something else */
 187#define CONFIG_ETHER_INDEX    2         /* which SCC/FCC channel for ethernet */
 188#else
 189#define CONFIG_ETHER_ON_SCC             /* define if ether on SCC       */
 190#undef  CONFIG_ETHER_ON_FCC             /* define if ether on FCC       */
 191#undef  CONFIG_ETHER_NONE               /* define if ether on something else */
 192#define CONFIG_ETHER_INDEX    1         /* which SCC/FCC channel for ethernet */
 193#endif
 194
 195#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
 196
 197/*
 198 *  - RX clk is CLK11
 199 *  - TX clk is CLK12
 200 */
 201# define CONFIG_SYS_CMXSCR_VALUE        (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
 202
 203#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
 204
 205/*
 206 * - Rx-CLK is CLK13
 207 * - Tx-CLK is CLK14
 208 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
 209 * - Enable Full Duplex in FSMR
 210 */
 211# define CONFIG_SYS_CMXFCR_MASK2        (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
 212# define CONFIG_SYS_CMXFCR_VALUE2       (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
 213# define CONFIG_SYS_CPMFCR_RAMTYPE      0
 214# define CONFIG_SYS_FCC_PSMR            (FCC_PSMR_FDE|FCC_PSMR_LPB)
 215
 216#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
 217
 218#define CONFIG_MII                      /* MII PHY management           */
 219#define CONFIG_BITBANGMII               /* bit-bang MII PHY management  */
 220/*
 221 * GPIO pins used for bit-banged MII communications
 222 */
 223#define MDIO_PORT       2               /* Port C */
 224#define MDIO_DECLARE    volatile ioport_t *iop = ioport_addr ( \
 225                                (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
 226#define MDC_DECLARE     MDIO_DECLARE
 227
 228#if STK82xx_150
 229#define CONFIG_SYS_MDIO_PIN     0x00008000      /* PC16 */
 230#define CONFIG_SYS_MDC_PIN      0x00004000      /* PC17 */
 231#endif
 232
 233#if STK82xx_100
 234#define CONFIG_SYS_MDIO_PIN     0x00000002      /* PC30 */
 235#define CONFIG_SYS_MDC_PIN      0x00000001      /* PC31 */
 236#endif
 237
 238#if 1
 239#define MDIO_ACTIVE     (iop->pdir |=  CONFIG_SYS_MDIO_PIN)
 240#define MDIO_TRISTATE   (iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
 241#define MDIO_READ       ((iop->pdat &  CONFIG_SYS_MDIO_PIN) != 0)
 242
 243#define MDIO(bit)       if(bit) iop->pdat |=  CONFIG_SYS_MDIO_PIN; \
 244                        else    iop->pdat &= ~CONFIG_SYS_MDIO_PIN
 245
 246#define MDC(bit)        if(bit) iop->pdat |=  CONFIG_SYS_MDC_PIN; \
 247                        else    iop->pdat &= ~CONFIG_SYS_MDC_PIN
 248#else
 249#define MDIO_ACTIVE     ({unsigned long tmp; tmp = iop->pdir; tmp |=  CONFIG_SYS_MDIO_PIN; iop->pdir = tmp;})
 250#define MDIO_TRISTATE   ({unsigned long tmp; tmp = iop->pdir; tmp &= ~CONFIG_SYS_MDIO_PIN; iop->pdir = tmp;})
 251#define MDIO_READ       ((iop->pdat &  CONFIG_SYS_MDIO_PIN) != 0)
 252
 253#define MDIO(bit)       if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |=  CONFIG_SYS_MDIO_PIN; iop->pdat = tmp;}\
 254                        else    {unsigned long tmp; tmp = iop->pdat; tmp &= ~CONFIG_SYS_MDIO_PIN; iop->pdat = tmp;}
 255
 256#define MDC(bit)        if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |=  CONFIG_SYS_MDC_PIN; iop->pdat = tmp;}\
 257                        else    {unsigned long tmp; tmp = iop->pdat; tmp &= ~CONFIG_SYS_MDC_PIN; iop->pdat = tmp;}
 258#endif
 259
 260#define MIIDELAY        udelay(1)
 261
 262
 263/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
 264#define CONFIG_8260_CLKIN       66666666        /* in Hz */
 265
 266#define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 267#undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
 268
 269#undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 270
 271#define CONFIG_TIMESTAMP                /* Print image info with timestamp */
 272
 273/*
 274 * BOOTP options
 275 */
 276#define CONFIG_BOOTP_SUBNETMASK
 277#define CONFIG_BOOTP_GATEWAY
 278#define CONFIG_BOOTP_HOSTNAME
 279#define CONFIG_BOOTP_BOOTPATH
 280#define CONFIG_BOOTP_BOOTFILESIZE
 281
 282
 283/*
 284 * Command line configuration.
 285 */
 286#include <config_cmd_default.h>
 287
 288#define CONFIG_CMD_I2C
 289#define CONFIG_CMD_DHCP
 290#define CONFIG_CMD_MII
 291#define CONFIG_CMD_NAND
 292#define CONFIG_CMD_NFS
 293#define CONFIG_CMD_PCI
 294#define CONFIG_CMD_PING
 295#define CONFIG_CMD_SNTP
 296
 297#if CONFIG_I2C
 298    #define CONFIG_CMD_I2C
 299    #define CONFIG_CMD_DATE
 300    #define CONFIG_CMD_DTT
 301    #define CONFIG_CMD_EEPROM
 302#endif
 303
 304
 305/*
 306 * Miscellaneous configurable options
 307 */
 308#define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 309#define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 310
 311#if 0
 312#define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 313#define CONFIG_SYS_HUSH_PARSER          1       /* Use the HUSH parser          */
 314#endif
 315
 316#if defined(CONFIG_CMD_KGDB)
 317#define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 318#else
 319#define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 320#endif
 321#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 322#define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 323#define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 324
 325#define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 326#define CONFIG_SYS_MEMTEST_END  0x0C00000       /* 4 ... 12 MB in DRAM  */
 327
 328#define CONFIG_SYS_LOAD_ADDR    0x300000        /* default load address */
 329
 330#define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 331
 332#define CONFIG_SYS_RESET_ADDRESS 0x40000104     /* "bad" address                */
 333
 334/*
 335 * For booting Linux, the board info and command line data
 336 * have to be in the first 8 MB of memory, since this is
 337 * the maximum mapped by the Linux kernel during initialization.
 338 */
 339#define CONFIG_SYS_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
 340
 341/*-----------------------------------------------------------------------
 342 * CAN stuff
 343 *-----------------------------------------------------------------------
 344 */
 345#define CONFIG_SYS_CAN_BASE     0x51000000
 346#define CONFIG_SYS_CAN_SIZE     1
 347#define CONFIG_SYS_CAN_BR       ((CONFIG_SYS_CAN_BASE & BRx_BA_MSK)     |\
 348                         BRx_PS_8                       |\
 349                         BRx_MS_UPMC                    |\
 350                         BRx_V)
 351
 352#define CONFIG_SYS_CAN_OR       (MEG_TO_AM(CONFIG_SYS_CAN_SIZE) |\
 353                         ORxU_BI)
 354
 355
 356/* What should the base address of the main FLASH be and how big is
 357 * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/tqm8272/config.mk
 358 * The main FLASH is whichever is connected to *CS0.
 359 */
 360#define CONFIG_SYS_FLASH0_BASE 0x40000000
 361#define CONFIG_SYS_FLASH0_SIZE 32       /* 32 MB */
 362
 363/* Flash bank size (for preliminary settings)
 364 */
 365#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
 366
 367/*-----------------------------------------------------------------------
 368 * FLASH organization
 369 */
 370#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks      */
 371#define CONFIG_SYS_MAX_FLASH_SECT       128     /* max num of sects on one chip */
 372
 373#define CONFIG_SYS_FLASH_CFI                            /* flash is CFI compat. */
 374#define CONFIG_FLASH_CFI_DRIVER                 /* Use common CFI driver*/
 375#define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector   */
 376#define CONFIG_SYS_FLASH_QUIET_TEST     1       /* don't warn upon unknown flash*/
 377
 378#define CONFIG_SYS_FLASH_ERASE_TOUT     240000  /* Flash Erase Timeout (in ms)  */
 379#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (in ms)  */
 380
 381#define CONFIG_SYS_UPDATE_FLASH_SIZE
 382
 383#define CONFIG_ENV_IS_IN_FLASH  1
 384#define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x40000)
 385#define CONFIG_ENV_SIZE         0x20000
 386#define CONFIG_ENV_SECT_SIZE    0x20000
 387#define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
 388#define CONFIG_ENV_SIZE_REDUND  0x20000
 389
 390/* Where is the Hardwareinformation Block (from Monitor Sources) */
 391#define MON_RES_LENGTH          (0x0003FC00)
 392#define HWIB_INFO_START_ADDR    (CONFIG_SYS_FLASH_BASE + MON_RES_LENGTH)
 393#define HWIB_INFO_LEN           512
 394#define CIB_INFO_START_ADDR     (CONFIG_SYS_FLASH_BASE + MON_RES_LENGTH + HWIB_INFO_LEN)
 395#define CIB_INFO_LEN            512
 396
 397#define CONFIG_SYS_HWINFO_OFFSET        0x3fc00 /* offset of HW Info block */
 398#define CONFIG_SYS_HWINFO_SIZE          0x00000060      /* size   of HW Info block */
 399#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38      /* 'TQM8' */
 400
 401/*-----------------------------------------------------------------------
 402 * NAND-FLASH stuff
 403 *-----------------------------------------------------------------------
 404 */
 405#if defined(CONFIG_CMD_NAND)
 406
 407#define CONFIG_SYS_NAND_CS_DIST         0x80
 408#define CONFIG_SYS_NAND_UPM_WRITE_CMD_OFS       0x20
 409#define CONFIG_SYS_NAND_UPM_WRITE_ADDR_OFS      0x40
 410
 411#define CONFIG_SYS_NAND_BR      ((CONFIG_SYS_NAND0_BASE & BRx_BA_MSK)   |\
 412                         BRx_PS_8                       |\
 413                         BRx_MS_UPMB                    |\
 414                         BRx_V)
 415
 416#define CONFIG_SYS_NAND_OR      (MEG_TO_AM(CONFIG_SYS_NAND_SIZE)        |\
 417                         ORxU_BI                        |\
 418                         ORxU_EHTR_8IDLE)
 419
 420#define CONFIG_SYS_NAND_SIZE    1
 421#define CONFIG_SYS_NAND0_BASE 0x50000000
 422#define CONFIG_SYS_NAND1_BASE (CONFIG_SYS_NAND0_BASE + CONFIG_SYS_NAND_CS_DIST)
 423#define CONFIG_SYS_NAND2_BASE (CONFIG_SYS_NAND1_BASE + CONFIG_SYS_NAND_CS_DIST)
 424#define CONFIG_SYS_NAND3_BASE (CONFIG_SYS_NAND2_BASE + CONFIG_SYS_NAND_CS_DIST)
 425
 426#define CONFIG_SYS_MAX_NAND_DEVICE     4       /* Max number of NAND devices           */
 427
 428#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, \
 429                             CONFIG_SYS_NAND1_BASE, \
 430                             CONFIG_SYS_NAND2_BASE, \
 431                             CONFIG_SYS_NAND3_BASE, \
 432                           }
 433
 434#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr)) = (__u8)d; } while(0)
 435#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr)))
 436#define WRITE_NAND_UPM(d, adr, off) do \
 437{ \
 438        volatile unsigned char *addr = (unsigned char *) (adr + off); \
 439        WRITE_NAND(d, addr); \
 440} while(0)
 441
 442#endif /* CONFIG_CMD_NAND */
 443
 444#define CONFIG_PCI
 445#ifdef CONFIG_PCI
 446#define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f      */
 447#define CONFIG_PCI_PNP
 448#define CONFIG_EEPRO100
 449#define CONFIG_SYS_RX_ETH_BUFFER        8               /* use 8 rx buffer on eepro100  */
 450#define CONFIG_PCI_SCAN_SHOW
 451#endif
 452
 453/*-----------------------------------------------------------------------
 454 * Hard Reset Configuration Words
 455 *
 456 * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
 457 * defines for the various registers affected by the HRCW e.g. changing
 458 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
 459 */
 460#if 0
 461#define __HRCW__ALL__           (HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
 462
 463#  define CONFIG_SYS_HRCW_MASTER        (__HRCW__ALL__ | HRCW_MODCK_H0111)
 464#else
 465#define CONFIG_SYS_HRCW_MASTER  (HRCW_BPS11 | HRCW_ISB111 | HRCW_BMS | HRCW_MODCK_H0111)
 466#endif
 467
 468/* no slaves so just fill with zeros */
 469#define CONFIG_SYS_HRCW_SLAVE1          0
 470#define CONFIG_SYS_HRCW_SLAVE2          0
 471#define CONFIG_SYS_HRCW_SLAVE3          0
 472#define CONFIG_SYS_HRCW_SLAVE4          0
 473#define CONFIG_SYS_HRCW_SLAVE5          0
 474#define CONFIG_SYS_HRCW_SLAVE6          0
 475#define CONFIG_SYS_HRCW_SLAVE7          0
 476
 477/*-----------------------------------------------------------------------
 478 * Internal Memory Mapped Register
 479 */
 480#define CONFIG_SYS_IMMR         0xFFF00000
 481
 482/*-----------------------------------------------------------------------
 483 * Definitions for initial stack pointer and data area (in DPRAM)
 484 */
 485#define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 486#define CONFIG_SYS_INIT_RAM_SIZE        0x2000  /* Size of used area in DPRAM    */
 487#define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 488#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 489
 490/*-----------------------------------------------------------------------
 491 * Start addresses for the final memory configuration
 492 * (Set up by the startup code)
 493 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 494 */
 495#define CONFIG_SYS_SDRAM_BASE           0x00000000
 496#define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_FLASH0_BASE
 497#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 498#define CONFIG_SYS_MONITOR_LEN          (192 << 10)     /* Reserve 192 kB for Monitor */
 499#define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()*/
 500
 501/*-----------------------------------------------------------------------
 502 * Cache Configuration
 503 */
 504#define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
 505#if defined(CONFIG_CMD_KGDB)
 506# define CONFIG_SYS_CACHELINE_SHIFT     5       /* log base 2 of the above value */
 507#endif
 508
 509/*-----------------------------------------------------------------------
 510 * HIDx - Hardware Implementation-dependent Registers                    2-11
 511 *-----------------------------------------------------------------------
 512 * HID0 also contains cache control - initially enable both caches and
 513 * invalidate contents, then the final state leaves only the instruction
 514 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 515 * but Soft reset does not.
 516 *
 517 * HID1 has only read-only information - nothing to set.
 518 */
 519#define CONFIG_SYS_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
 520                                HID0_IFEM|HID0_ABE)
 521#define CONFIG_SYS_HID0_FINAL  (HID0_IFEM|HID0_ABE)
 522#define CONFIG_SYS_HID2        0
 523
 524/*-----------------------------------------------------------------------
 525 * RMR - Reset Mode Register                                     5-5
 526 *-----------------------------------------------------------------------
 527 * turn on Checkstop Reset Enable
 528 */
 529#define CONFIG_SYS_RMR         RMR_CSRE
 530
 531/*-----------------------------------------------------------------------
 532 * BCR - Bus Configuration                                       4-25
 533 *-----------------------------------------------------------------------
 534 */
 535#define CONFIG_SYS_BCR_60x         (BCR_EBM|BCR_NPQM0|BCR_NPQM2)        /* 60x mode  */
 536#define BCR_APD01       0x10000000
 537#define CONFIG_SYS_BCR_SINGLE           (BCR_APD01|BCR_ETM)     /* 8260 mode */
 538
 539/*-----------------------------------------------------------------------
 540 * SIUMCR - SIU Module Configuration                             4-31
 541 *-----------------------------------------------------------------------
 542 */
 543#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
 544#define CONFIG_SYS_SIUMCR_LOW           (SIUMCR_DPPC00)
 545#define CONFIG_SYS_SIUMCR_HIGH          (SIUMCR_DPPC00 | SIUMCR_ABE)
 546#else
 547#define CONFIG_SYS_SIUMCR               (SIUMCR_DPPC00)
 548#endif
 549
 550/*-----------------------------------------------------------------------
 551 * SYPCR - System Protection Control                             4-35
 552 * SYPCR can only be written once after reset!
 553 *-----------------------------------------------------------------------
 554 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 555 */
 556#if defined(CONFIG_WATCHDOG)
 557#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 558                         SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 559#else
 560#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 561                         SYPCR_SWRI|SYPCR_SWP)
 562#endif /* CONFIG_WATCHDOG */
 563
 564/*-----------------------------------------------------------------------
 565 * TMCNTSC - Time Counter Status and Control                     4-40
 566 *-----------------------------------------------------------------------
 567 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 568 * and enable Time Counter
 569 */
 570#define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 571
 572/*-----------------------------------------------------------------------
 573 * PISCR - Periodic Interrupt Status and Control                 4-42
 574 *-----------------------------------------------------------------------
 575 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 576 * Periodic timer
 577 */
 578#define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 579
 580/*-----------------------------------------------------------------------
 581 * SCCR - System Clock Control                                   9-8
 582 *-----------------------------------------------------------------------
 583 * Ensure DFBRG is Divide by 16
 584 */
 585#define CONFIG_SYS_SCCR        SCCR_DFBRG01
 586
 587/*-----------------------------------------------------------------------
 588 * RCCR - RISC Controller Configuration                         13-7
 589 *-----------------------------------------------------------------------
 590 */
 591#define CONFIG_SYS_RCCR        0
 592
 593/*
 594 * Init Memory Controller:
 595 *
 596 * Bank Bus     Machine PortSz  Device
 597 * ---- ---     ------- ------  ------
 598 *  0   60x     GPCM    32 bit  FLASH
 599 *  1   60x     SDRAM   64 bit  SDRAM
 600 *  2   60x     UPMB     8 bit  NAND
 601 *  3   60x     UPMC     8 bit  CAN
 602 *
 603 */
 604
 605/* Initialize SDRAM
 606         */
 607#undef CONFIG_SYS_INIT_LOCAL_SDRAM              /* No SDRAM on Local Bus */
 608
 609#define SDRAM_MAX_SIZE  0x20000000      /* max. 512 MB          */
 610
 611/* Minimum mask to separate preliminary
 612 * address ranges for CS[0:2]
 613 */
 614#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT   (512<<20)       /* less than 512 MB */
 615
 616#define CONFIG_SYS_MPTPR       0x4000
 617
 618/*-----------------------------------------------------------------------------
 619 * Address for Mode Register Set (MRS) command
 620 *-----------------------------------------------------------------------------
 621 * In fact, the address is rather configuration data presented to the SDRAM on
 622 * its address lines. Because the address lines may be mux'ed externally either
 623 * for 8 column or 9 column devices, some bits appear twice in the 8260's
 624 * address:
 625 *
 626 * |   (RFU)   |   (RFU)   | WBL |    TM    |     CL    |  BT | Burst Length |
 627 * | BA1   BA0 | A12 : A10 |  A9 |  A8   A7 |  A6 : A4  |  A3 |   A2 :  A0   |
 628 *  8 columns mux'ing:     |  A9 | A10  A21 | A22 : A24 | A25 |  A26 : A28   |
 629 *  9 columns mux'ing:     |  A8 | A20  A21 | A22 : A24 | A25 |  A26 : A28   |
 630 *  Settings:              |  0  |  0    0  |  0  1  0  |  0  |   0  1  0    |
 631 *-----------------------------------------------------------------------------
 632 */
 633#define CONFIG_SYS_MRS_OFFS     0x00000110
 634
 635/* Bank 0 - FLASH
 636 */
 637#define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
 638                         BRx_PS_32                      |\
 639                         BRx_MS_GPCM_P                  |\
 640                         BRx_V)
 641
 642#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE)      |\
 643                         ORxG_CSNT                      |\
 644                         ORxG_ACS_DIV4                  |\
 645                         ORxG_SCY_8_CLK                 |\
 646                         ORxG_TRLX)
 647
 648/* SDRAM on TQM8272 can have either 8 or 9 columns.
 649 * The number affects configuration values.
 650 */
 651
 652/* Bank 1 - 60x bus SDRAM
 653 */
 654#define CONFIG_SYS_PSRT        0x20     /* Low Value */
 655/* #define CONFIG_SYS_PSRT        0x10   Fast Value */
 656#define CONFIG_SYS_LSRT        0x20     /* Local Bus */
 657#ifndef CONFIG_SYS_RAMBOOT
 658#define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
 659                         BRx_PS_64                      |\
 660                         BRx_MS_SDRAM_P                 |\
 661                         BRx_V)
 662
 663#define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR1_8COL
 664
 665/* SDRAM initialization values for 8-column chips
 666 */
 667#define CONFIG_SYS_OR1_8COL    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 668                         ORxS_BPD_4                     |\
 669                         ORxS_ROWST_PBI1_A7             |\
 670                         ORxS_NUMR_12)
 671
 672#define CONFIG_SYS_PSDMR_8COL  (PSDMR_PBI                      |\
 673                         PSDMR_SDAM_A15_IS_A5           |\
 674                         PSDMR_BSMA_A12_A14             |\
 675                         PSDMR_SDA10_PBI1_A8            |\
 676                         PSDMR_RFRC_7_CLK               |\
 677                         PSDMR_PRETOACT_2W              |\
 678                         PSDMR_ACTTORW_2W               |\
 679                         PSDMR_LDOTOPRE_1C              |\
 680                         PSDMR_WRC_2C                   |\
 681                         PSDMR_EAMUX                    |\
 682                         PSDMR_BUFCMD                   |\
 683                         PSDMR_CL_2)
 684
 685
 686/* SDRAM initialization values for 9-column chips
 687 */
 688#define CONFIG_SYS_OR1_9COL    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 689                         ORxS_BPD_4                     |\
 690                         ORxS_ROWST_PBI1_A5             |\
 691                         ORxS_NUMR_13)
 692
 693#define CONFIG_SYS_PSDMR_9COL  (PSDMR_PBI                      |\
 694                         PSDMR_SDAM_A16_IS_A5           |\
 695                         PSDMR_BSMA_A12_A14             |\
 696                         PSDMR_SDA10_PBI1_A7            |\
 697                         PSDMR_RFRC_7_CLK               |\
 698                         PSDMR_PRETOACT_2W              |\
 699                         PSDMR_ACTTORW_2W               |\
 700                         PSDMR_LDOTOPRE_1C              |\
 701                         PSDMR_WRC_2C                   |\
 702                         PSDMR_EAMUX                    |\
 703                         PSDMR_BUFCMD                   |\
 704                         PSDMR_CL_2)
 705
 706#define CONFIG_SYS_OR1_10COL    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 707                         ORxS_BPD_4                     |\
 708                         ORxS_ROWST_PBI1_A4             |\
 709                         ORxS_NUMR_13)
 710
 711#define CONFIG_SYS_PSDMR_10COL  (PSDMR_PBI                      |\
 712                         PSDMR_SDAM_A17_IS_A5           |\
 713                         PSDMR_BSMA_A12_A14             |\
 714                         PSDMR_SDA10_PBI1_A4            |\
 715                         PSDMR_RFRC_6_CLK               |\
 716                         PSDMR_PRETOACT_2W              |\
 717                         PSDMR_ACTTORW_2W               |\
 718                         PSDMR_LDOTOPRE_1C              |\
 719                         PSDMR_WRC_2C                   |\
 720                         PSDMR_EAMUX                    |\
 721                         PSDMR_BUFCMD                   |\
 722                         PSDMR_CL_2)
 723
 724#define PSDMR_RFRC_66MHZ_SINGLE         0x00028000  /* PSDMR[RFRC] at 66 MHz single mode */
 725#define PSDMR_RFRC_100MHZ_SINGLE        0x00030000  /* PSDMR[RFRC] at 100 MHz single mode */
 726#define PSDMR_RFRC_133MHZ_SINGLE        0x00030000  /* PSDMR[RFRC] at 133 MHz single mode */
 727#define PSDMR_RFRC_66MHZ_60X            0x00030000  /* PSDMR[RFRC] at 66 MHz 60x mode */
 728#define PSDMR_RFRC_100MHZ_60X           0x00028000  /* PSDMR[RFRC] at 100 MHz 60x mode */
 729#define PSDMR_RFRC_DEFAULT              PSDMR_RFRC_133MHZ_SINGLE  /* PSDMR[RFRC] default value */
 730
 731#define PSDMR_PRETOACT_66MHZ_SINGLE     0x00002000  /* PSDMR[PRETOACT] at 66 MHz single mode */
 732#define PSDMR_PRETOACT_100MHZ_SINGLE    0x00002000  /* PSDMR[PRETOACT] at 100 MHz single mode */
 733#define PSDMR_PRETOACT_133MHZ_SINGLE    0x00002000  /* PSDMR[PRETOACT] at 133 MHz single mode */
 734#define PSDMR_PRETOACT_66MHZ_60X        0x00001000  /* PSDMR[PRETOACT] at 66 MHz 60x mode */
 735#define PSDMR_PRETOACT_100MHZ_60X       0x00001000  /* PSDMR[PRETOACT] at 100 MHz 60x mode */
 736#define PSDMR_PRETOACT_DEFAULT          PSDMR_PRETOACT_133MHZ_SINGLE  /* PSDMR[PRETOACT] default value */
 737
 738#define PSDMR_WRC_66MHZ_SINGLE          0x00000020  /* PSDMR[WRC] at 66 MHz single mode */
 739#define PSDMR_WRC_100MHZ_SINGLE         0x00000020  /* PSDMR[WRC] at 100 MHz single mode */
 740#define PSDMR_WRC_133MHZ_SINGLE         0x00000010  /* PSDMR[WRC] at 133 MHz single mode */
 741#define PSDMR_WRC_66MHZ_60X             0x00000010  /* PSDMR[WRC] at 66 MHz 60x mode */
 742#define PSDMR_WRC_100MHZ_60X            0x00000010  /* PSDMR[WRC] at 100 MHz 60x mode */
 743#define PSDMR_WRC_DEFAULT               PSDMR_WRC_133MHZ_SINGLE  /* PSDMR[WRC] default value */
 744
 745#define PSDMR_BUFCMD_66MHZ_SINGLE       0x00000000  /* PSDMR[BUFCMD] at 66 MHz single mode */
 746#define PSDMR_BUFCMD_100MHZ_SINGLE      0x00000000  /* PSDMR[BUFCMD] at 100 MHz single mode */
 747#define PSDMR_BUFCMD_133MHZ_SINGLE      0x00000004  /* PSDMR[BUFCMD] at 133 MHz single mode */
 748#define PSDMR_BUFCMD_66MHZ_60X          0x00000000  /* PSDMR[BUFCMD] at 66 MHz 60x mode */
 749#define PSDMR_BUFCMD_100MHZ_60X         0x00000000  /* PSDMR[BUFCMD] at 100 MHz 60x mode */
 750#define PSDMR_BUFCMD_DEFAULT            PSDMR_BUFCMD_133MHZ_SINGLE  /* PSDMR[BUFCMD] default value */
 751
 752#endif /* CONFIG_SYS_RAMBOOT */
 753
 754#endif  /* __CONFIG_H */
 755