LXR uboot/include/configs/dlvision-10g.h

   1/*
   2 * (C) Copyright 2010
   3 * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24#ifndef __CONFIG_H
  25#define __CONFIG_H
  26
  27#define CONFIG_405EP            1       /* this is a PPC405 CPU */
  28#define CONFIG_4xx              1       /*  member of PPC4xx family */
  29#define CONFIG_DLVISION_10G     1       /*  on a DLVision-10G board */
  30
  31#define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  32
  33/*
  34 * Include common defines/options for all AMCC eval boards
  35 */
  36#define CONFIG_HOSTNAME         dlvsion-10g
  37#define CONFIG_IDENT_STRING     " dlvision-10g 0.03"
  38#include "amcc-common.h"
  39
  40#define CONFIG_BOARD_EARLY_INIT_F
  41#define CONFIG_BOARD_EARLY_INIT_R
  42#define CONFIG_MISC_INIT_R
  43#define CONFIG_LAST_STAGE_INIT
  44
  45#define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
  46
  47#undef CONFIG_ZERO_BOOTDELAY_CHECK     /* ignore keypress on bootdelay==0 */
  48#define CONFIG_AUTOBOOT_KEYED          /* use key strings to stop autoboot */
  49#define CONFIG_AUTOBOOT_STOP_STR " "
  50
  51/*
  52 * Configure PLL
  53 */
  54#define PLLMR0_DEFAULT PLLMR0_266_133_66
  55#define PLLMR1_DEFAULT PLLMR1_266_133_66
  56
  57/* new uImage format support */
  58#define CONFIG_FIT
  59#define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
  60
  61#define CONFIG_ENV_IS_IN_FLASH  /* use FLASH for environment vars */
  62
  63/*
  64 * Default environment variables
  65 */
  66#define CONFIG_EXTRA_ENV_SETTINGS                                       \
  67        CONFIG_AMCC_DEF_ENV                                             \
  68        CONFIG_AMCC_DEF_ENV_POWERPC                                     \
  69        CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
  70        "kernel_addr=fc000000\0"                                        \
  71        "fdt_addr=fc1e0000\0"                                           \
  72        "ramdisk_addr=fc200000\0"                                       \
  73        ""
  74
  75#define CONFIG_PHY_ADDR         4       /* PHY address                  */
  76#define CONFIG_HAS_ETH0
  77#define CONFIG_HAS_ETH1
  78#define CONFIG_PHY1_ADDR        0xc     /* EMAC1 PHY address            */
  79#define CONFIG_PHY_CLK_FREQ     EMAC_STACR_CLK_66MHZ
  80
  81/*
  82 * Commands additional to the ones defined in amcc-common.h
  83 */
  84#define CONFIG_CMD_CACHE
  85#define CONFIG_CMD_DTT
  86#undef CONFIG_CMD_EEPROM
  87
  88/*
  89 * SDRAM configuration (please see cpu/ppc/sdram.[ch])
  90 */
  91#define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0 */
  92
  93/* SDRAM timings used in datasheet */
  94#define CONFIG_SYS_SDRAM_CL             3       /* CAS latency */
  95#define CONFIG_SYS_SDRAM_tRP           20       /* PRECHARGE command period */
  96#define CONFIG_SYS_SDRAM_tRC           66       /* ACTIVE-to-ACTIVE period */
  97#define CONFIG_SYS_SDRAM_tRCD          20       /* ACTIVE-to-READ delay */
  98#define CONFIG_SYS_SDRAM_tRFC          66       /* Auto refresh period */
  99
 100/*
 101 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
 102 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
 103 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
 104 * The Linux BASE_BAUD define should match this configuration.
 105 *    baseBaud = cpuClock/(uartDivisor*16)
 106 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
 107 * set Linux BASE_BAUD to 403200.
 108 */
 109#define CONFIG_CONS_INDEX       1       /* Use UART0                    */
 110#undef  CONFIG_SYS_EXT_SERIAL_CLOCK     /* external serial clock */
 111#undef  CONFIG_SYS_405_UART_ERRATA_59   /* 405GP/CR Rev. D silicon */
 112#define CONFIG_SYS_BASE_BAUD            691200
 113
 114/*
 115 * I2C stuff
 116 */
 117#define CONFIG_SYS_I2C_SPEED            100000
 118
 119/* Temp sensor/hwmon/dtt */
 120#define CONFIG_DTT_LM63         1       /* National LM63        */
 121#define CONFIG_DTT_SENSORS      { 0x4c, 0x4e, 0x18 } /* Sensor addresses */
 122#define CONFIG_DTT_PWM_LOOKUPTABLE      \
 123                { { 46, 10 }, { 48, 14 }, { 50, 19 }, { 52, 23 },\
 124                  { 54, 27 }, { 56, 31 }, { 58, 36 }, { 60, 40 } }
 125#define CONFIG_DTT_TACH_LIMIT   0xa10
 126
 127/* EBC peripherals */
 128
 129#define CONFIG_SYS_FLASH_BASE           0xFC000000
 130#define CONFIG_SYS_FPGA0_BASE           0x7f100000
 131#define CONFIG_SYS_FPGA1_BASE           0x7f200000
 132#define CONFIG_SYS_LATCH_BASE           0x7f300000
 133
 134#define CONFIG_SYS_FPGA_BASE(k) \
 135        (k ? CONFIG_SYS_FPGA1_BASE : CONFIG_SYS_FPGA0_BASE)
 136
 137#define CONFIG_SYS_FPGA_DONE(k) \
 138        (k ? 0x2000 : 0x1000)
 139
 140#define CONFIG_SYS_FPGA_COUNT           2
 141
 142#define CONFIG_SYS_LATCH0_RESET         0xffff
 143#define CONFIG_SYS_LATCH0_BOOT          0xffff
 144#define CONFIG_SYS_LATCH1_RESET         0xffcf
 145#define CONFIG_SYS_LATCH1_BOOT          0xffff
 146
 147#define CONFIG_SYS_FPGA_NO_RFL_HI
 148
 149/*
 150 * FLASH organization
 151 */
 152#define CONFIG_SYS_FLASH_CFI            /* The flash is CFI compatible  */
 153#define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
 154
 155#define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 156
 157#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks */
 158#define CONFIG_SYS_MAX_FLASH_SECT       512     /* max num of sectors per chip*/
 159
 160#define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase/ms */
 161#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write/ms */
 162
 163#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buff'd writes */
 164#define CONFIG_SYS_FLASH_PROTECTION     1       /* use hardware flash protect */
 165
 166#define CONFIG_SYS_FLASH_EMPTY_INFO     /* 'E' for empty sector on flinfo */
 167#define CONFIG_SYS_FLASH_QUIET_TEST     1       /* no warn upon unknown flash */
 168
 169#ifdef CONFIG_ENV_IS_IN_FLASH
 170#define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector */
 171#define CONFIG_ENV_ADDR         ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
 172#define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector */
 173
 174/* Address and size of Redundant Environment Sector     */
 175#define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 176#define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 177#endif
 178
 179/*
 180 * PPC405 GPIO Configuration
 181 */
 182#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO     Alternate1      */ \
 183{ \
 184/* GPIO Core 0 */ \
 185{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO0   PerBLast */ \
 186{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO1   TS1E */ \
 187{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO2   TS2E */ \
 188{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO3   TS1O */ \
 189{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO4   TS2O */ \
 190{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO5   TS3 */ \
 191{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO6   TS4 */ \
 192{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO7   TS5 */ \
 193{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO8   TS6 */ \
 194{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO9   TrcClk */ \
 195{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10  PerCS1 */ \
 196{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11  PerCS2 */ \
 197{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12  PerCS3 */ \
 198{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO13  PerCS4 */ \
 199{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14  PerAddr03 */ \
 200{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15  PerAddr04 */ \
 201{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16  PerAddr05 */ \
 202{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17  IRQ0 */ \
 203{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18  IRQ1 */ \
 204{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19  IRQ2 */ \
 205{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO20  IRQ3 */ \
 206{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO21  IRQ4 */ \
 207{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO22  IRQ5 */ \
 208{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO23  IRQ6 */ \
 209{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24  UART0_DCD */ \
 210{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25  UART0_DSR */ \
 211{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26  UART0_RI */ \
 212{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27  UART0_DTR */ \
 213{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28  UART1_Rx */ \
 214{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29  UART1_Tx */ \
 215{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30  RejectPkt0 */ \
 216{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31  RejectPkt1 */ \
 217} \
 218}
 219
 220/*
 221 * Definitions for initial stack pointer and data area (in data cache)
 222 */
 223/* use on chip memory (OCM) for temperary stack until sdram is tested */
 224#define CONFIG_SYS_TEMP_STACK_OCM       1
 225
 226/* On Chip Memory location */
 227#define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 228#define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 229#define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
 230#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
 231
 232#define CONFIG_SYS_GBL_DATA_SIZE        128  /* size/bytes res'd for init data*/
 233#define CONFIG_SYS_GBL_DATA_OFFSET \
 234        (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 235#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 236
 237/*
 238 * External Bus Controller (EBC) Setup
 239 */
 240
 241/* Memory Bank 0 (NOR-flash) */
 242#define CONFIG_SYS_EBC_PB0AP    (EBC_BXAP_BME_ENABLED           |       \
 243                                 EBC_BXAP_FWT_ENCODE(8)         |       \
 244                                 EBC_BXAP_BWT_ENCODE(7)         |       \
 245                                 EBC_BXAP_BCE_DISABLE           |       \
 246                                 EBC_BXAP_BCT_2TRANS            |       \
 247                                 EBC_BXAP_CSN_ENCODE(0)         |       \
 248                                 EBC_BXAP_OEN_ENCODE(2)         |       \
 249                                 EBC_BXAP_WBN_ENCODE(2)         |       \
 250                                 EBC_BXAP_WBF_ENCODE(2)         |       \
 251                                 EBC_BXAP_TH_ENCODE(4)          |       \
 252                                 EBC_BXAP_RE_DISABLED           |       \
 253                                 EBC_BXAP_SOR_NONDELAYED        |       \
 254                                 EBC_BXAP_BEM_WRITEONLY         |       \
 255                                 EBC_BXAP_PEN_DISABLED)
 256#define CONFIG_SYS_EBC_PB0CR    (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
 257                                 EBC_BXCR_BS_64MB               |       \
 258                                 EBC_BXCR_BU_RW                 |       \
 259                                 EBC_BXCR_BW_16BIT)
 260
 261/* Memory Bank 1 (FPGA0) */
 262#define CONFIG_SYS_EBC_PB1AP    (EBC_BXAP_BME_DISABLED          |       \
 263                                 EBC_BXAP_TWT_ENCODE(5)         |       \
 264                                 EBC_BXAP_BCE_DISABLE           |       \
 265                                 EBC_BXAP_BCT_2TRANS            |       \
 266                                 EBC_BXAP_CSN_ENCODE(0)         |       \
 267                                 EBC_BXAP_OEN_ENCODE(2)         |       \
 268                                 EBC_BXAP_WBN_ENCODE(1)         |       \
 269                                 EBC_BXAP_WBF_ENCODE(1)         |       \
 270                                 EBC_BXAP_TH_ENCODE(0)          |       \
 271                                 EBC_BXAP_RE_DISABLED           |       \
 272                                 EBC_BXAP_SOR_NONDELAYED        |       \
 273                                 EBC_BXAP_BEM_WRITEONLY         |       \
 274                                 EBC_BXAP_PEN_DISABLED)
 275#define CONFIG_SYS_EBC_PB1CR    (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA0_BASE) | \
 276                                 EBC_BXCR_BS_1MB                |       \
 277                                 EBC_BXCR_BU_RW                 |       \
 278                                 EBC_BXCR_BW_16BIT)
 279
 280/* Memory Bank 2 (FPGA1) */
 281#define CONFIG_SYS_EBC_PB2AP    (EBC_BXAP_BME_DISABLED          |       \
 282                                 EBC_BXAP_TWT_ENCODE(6)         |       \
 283                                 EBC_BXAP_BCE_DISABLE           |       \
 284                                 EBC_BXAP_BCT_2TRANS            |       \
 285                                 EBC_BXAP_CSN_ENCODE(0)         |       \
 286                                 EBC_BXAP_OEN_ENCODE(2)         |       \
 287                                 EBC_BXAP_WBN_ENCODE(1)         |       \
 288                                 EBC_BXAP_WBF_ENCODE(1)         |       \
 289                                 EBC_BXAP_TH_ENCODE(0)          |       \
 290                                 EBC_BXAP_RE_DISABLED           |       \
 291                                 EBC_BXAP_SOR_NONDELAYED        |       \
 292                                 EBC_BXAP_BEM_WRITEONLY         |       \
 293                                 EBC_BXAP_PEN_DISABLED)
 294#define CONFIG_SYS_EBC_PB2CR    (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA1_BASE) | \
 295                                 EBC_BXCR_BS_1MB                |       \
 296                                 EBC_BXCR_BU_RW                 |       \
 297                                 EBC_BXCR_BW_16BIT)
 298
 299/* Memory Bank 3 (Latches) */
 300#define CONFIG_SYS_EBC_PB3AP    (EBC_BXAP_BME_ENABLED           |       \
 301                                 EBC_BXAP_FWT_ENCODE(8)         |       \
 302                                 EBC_BXAP_BWT_ENCODE(4)         |       \
 303                                 EBC_BXAP_BCE_DISABLE           |       \
 304                                 EBC_BXAP_BCT_2TRANS            |       \
 305                                 EBC_BXAP_CSN_ENCODE(0)         |       \
 306                                 EBC_BXAP_OEN_ENCODE(1)         |       \
 307                                 EBC_BXAP_WBN_ENCODE(1)         |       \
 308                                 EBC_BXAP_WBF_ENCODE(1)         |       \
 309                                 EBC_BXAP_TH_ENCODE(2)          |       \
 310                                 EBC_BXAP_RE_DISABLED           |       \
 311                                 EBC_BXAP_SOR_NONDELAYED        |       \
 312                                 EBC_BXAP_BEM_WRITEONLY         |       \
 313                                 EBC_BXAP_PEN_DISABLED)
 314#define CONFIG_SYS_EBC_PB3CR    (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_LATCH_BASE) | \
 315                                 EBC_BXCR_BS_1MB                |       \
 316                                 EBC_BXCR_BU_RW                 |       \
 317                                 EBC_BXCR_BW_16BIT)
 318
 319/*
 320 * OSD Setup
 321 */
 322#define CONFIG_SYS_ICS8N3QV01
 323#define CONFIG_SYS_MPC92469AC
 324#define CONFIG_SYS_SIL1178
 325#define CONFIG_SYS_OSD_SCREENS          CONFIG_SYS_FPGA_COUNT
 326
 327#endif  /* __CONFIG_H */
 328