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23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27#define CONFIG_405EP 1
28#define CONFIG_4xx 1
29#define CONFIG_IOCON 1
30
31#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
32
33
34
35
36#define CONFIG_HOSTNAME iocon
37#define CONFIG_IDENT_STRING " iocon 0.04"
38#include "amcc-common.h"
39
40#define CONFIG_BOARD_EARLY_INIT_F
41#define CONFIG_BOARD_EARLY_INIT_R
42#define CONFIG_LAST_STAGE_INIT
43
44#define CONFIG_SYS_CLK_FREQ 33333333
45
46
47
48
49#define PLLMR0_DEFAULT PLLMR0_266_133_66
50#define PLLMR1_DEFAULT PLLMR1_266_133_66
51
52#undef CONFIG_ZERO_BOOTDELAY_CHECK
53#define CONFIG_AUTOBOOT_KEYED
54#define CONFIG_AUTOBOOT_STOP_STR " "
55
56
57#define CONFIG_FIT
58#define CONFIG_FIT_VERBOSE
59
60#define CONFIG_ENV_IS_IN_FLASH
61
62
63
64
65#define CONFIG_EXTRA_ENV_SETTINGS \
66 CONFIG_AMCC_DEF_ENV \
67 CONFIG_AMCC_DEF_ENV_POWERPC \
68 CONFIG_AMCC_DEF_ENV_NOR_UPD \
69 "kernel_addr=fc000000\0" \
70 "fdt_addr=fc1e0000\0" \
71 "ramdisk_addr=fc200000\0" \
72 ""
73
74#define CONFIG_PHY_ADDR 4
75#define CONFIG_HAS_ETH0
76#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
77
78
79
80
81#define CONFIG_CMD_CACHE
82#undef CONFIG_CMD_EEPROM
83
84
85
86
87#define CONFIG_SDRAM_BANK0 1
88
89
90#define CONFIG_SYS_SDRAM_CL 3
91#define CONFIG_SYS_SDRAM_tRP 20
92#define CONFIG_SYS_SDRAM_tRC 66
93#define CONFIG_SYS_SDRAM_tRCD 20
94#define CONFIG_SYS_SDRAM_tRFC 66
95
96
97
98
99
100
101
102
103
104
105#define CONFIG_CONS_INDEX 1
106#undef CONFIG_SYS_EXT_SERIAL_CLOCK
107#undef CONFIG_SYS_405_UART_ERRATA_59
108#define CONFIG_SYS_BASE_BAUD 691200
109
110
111
112
113#define CONFIG_SYS_I2C_SPEED 400000
114
115
116#undef CONFIG_HARD_I2C
117#define CONFIG_SOFT_I2C 1
118
119
120
121
122
123#ifndef __ASSEMBLY__
124void fpga_gpio_set(int pin);
125void fpga_gpio_clear(int pin);
126int fpga_gpio_get(int pin);
127#endif
128
129#define I2C_ACTIVE { }
130#define I2C_TRISTATE { }
131#define I2C_READ fpga_gpio_get(0x0040) ? 1 : 0
132#define I2C_SDA(bit) if (bit) fpga_gpio_set(0x0040); \
133 else fpga_gpio_clear(0x0040)
134#define I2C_SCL(bit) if (bit) fpga_gpio_set(0x0020); \
135 else fpga_gpio_clear(0x0020)
136#define I2C_DELAY udelay(25)
137
138
139
140
141#define CONFIG_SYS_MPC92469AC
142#define CONFIG_SYS_CH7301
143
144
145
146
147#define CONFIG_SYS_FLASH_CFI
148#define CONFIG_FLASH_CFI_DRIVER
149
150#define CONFIG_SYS_FLASH_BASE 0xFC000000
151#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
152
153#define CONFIG_SYS_MAX_FLASH_BANKS 1
154#define CONFIG_SYS_MAX_FLASH_SECT 512
155
156#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
157#define CONFIG_SYS_FLASH_WRITE_TOUT 500
158
159#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
160#define CONFIG_SYS_FLASH_PROTECTION 1
161
162#define CONFIG_SYS_FLASH_EMPTY_INFO
163#define CONFIG_SYS_FLASH_QUIET_TEST 1
164
165#ifdef CONFIG_ENV_IS_IN_FLASH
166#define CONFIG_ENV_SECT_SIZE 0x20000
167#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
168#define CONFIG_ENV_SIZE 0x2000
169
170
171#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
172#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
173#endif
174
175
176
177
178#define CONFIG_SYS_4xx_GPIO_TABLE { \
179{ \
180 \
181{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
182{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
183{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
184{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
185{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
186{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, \
187{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
188{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
189{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
190{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
191{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
192{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
193{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
194{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
195{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
196{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
197{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
198{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
199{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
200{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
201{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
202{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
203{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
204{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
205{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
206{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
207{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
208{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
209{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
210{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
211{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
212{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
213} \
214}
215
216
217
218
219
220#define CONFIG_SYS_TEMP_STACK_OCM 1
221
222
223#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
224#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
225#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
226#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE
227
228#define CONFIG_SYS_GBL_DATA_SIZE 128
229#define CONFIG_SYS_GBL_DATA_OFFSET \
230 (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
231#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
232
233
234
235
236
237
238#define CONFIG_SYS_EBC_PB0AP 0xa382a880
239#define CONFIG_SYS_EBC_PB0CR 0xFC0DA000
240
241
242#define CONFIG_SYS_EBC_PB1AP 0x92015480
243#define CONFIG_SYS_EBC_PB1CR 0xFB858000
244
245
246#define CONFIG_SYS_FPGA0_BASE 0x7f100000
247#define CONFIG_SYS_EBC_PB2AP 0x02825080
248#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA0_BASE | 0x1a000)
249
250#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
251#define CONFIG_SYS_FPGA_DONE(k) 0x0010
252
253#define CONFIG_SYS_FPGA_COUNT 1
254
255
256#define CONFIG_SYS_LATCH_BASE 0x7f200000
257#define CONFIG_SYS_EBC_PB3AP 0x02025080
258#define CONFIG_SYS_EBC_PB3CR 0x7f21a000
259
260#define CONFIG_SYS_LATCH0_RESET 0xffef
261#define CONFIG_SYS_LATCH0_BOOT 0xffff
262#define CONFIG_SYS_LATCH1_RESET 0xffff
263#define CONFIG_SYS_LATCH1_BOOT 0xffff
264
265
266
267
268#define CONFIG_SYS_MPC92469AC
269#define CONFIG_SYS_CH7301
270#define CONFIG_SYS_OSD_SCREENS CONFIG_SYS_FPGA_COUNT
271
272#endif
273