LXR uboot/include/linux/mtd/samsung

   1/*
   2 *  Copyright (C) 2005-2009 Samsung Electronics
   3 *  Minkyu Kang <mk7.kang@samsung.com>
   4 *  Kyungmin Park <kyungmin.park@samsung.com>
   5 *
   6 * See file CREDITS for list of people who contributed to this
   7 * project.
   8 *
   9 * This program is free software; you can redistribute it and/or
  10 * modify it under the terms of the GNU General Public License as
  11 * published by the Free Software Foundation; either version 2 of
  12 * the License, or (at your option) any later version.
  13 *
  14 * This program is distributed in the hope that it will be useful,
  15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 * GNU General Public License for more details.
  18 *
  19 * You should have received a copy of the GNU General Public License
  20 * along with this program; if not, write to the Free Software
  21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22 * MA 02111-1307 USA
  23 */
  24
  25#ifndef __SAMSUNG_ONENAND_H__
  26#define __SAMSUNG_ONENAND_H__
  27
  28/*
  29 * OneNAND Controller
  30 */
  31
  32#ifndef __ASSEMBLY__
  33struct samsung_onenand {
  34        unsigned int    mem_cfg;        /* 0x0000 */
  35        unsigned char   res1[0xc];
  36        unsigned int    burst_len;      /* 0x0010 */
  37        unsigned char   res2[0xc];
  38        unsigned int    mem_reset;      /* 0x0020 */
  39        unsigned char   res3[0xc];
  40        unsigned int    int_err_stat;   /* 0x0030 */
  41        unsigned char   res4[0xc];
  42        unsigned int    int_err_mask;   /* 0x0040 */
  43        unsigned char   res5[0xc];
  44        unsigned int    int_err_ack;    /* 0x0050 */
  45        unsigned char   res6[0xc];
  46        unsigned int    ecc_err_stat;   /* 0x0060 */
  47        unsigned char   res7[0xc];
  48        unsigned int    manufact_id;    /* 0x0070 */
  49        unsigned char   res8[0xc];
  50        unsigned int    device_id;      /* 0x0080 */
  51        unsigned char   res9[0xc];
  52        unsigned int    data_buf_size;  /* 0x0090 */
  53        unsigned char   res10[0xc];
  54        unsigned int    boot_buf_size;  /* 0x00A0 */
  55        unsigned char   res11[0xc];
  56        unsigned int    buf_amount;     /* 0x00B0 */
  57        unsigned char   res12[0xc];
  58        unsigned int    tech;           /* 0x00C0 */
  59        unsigned char   res13[0xc];
  60        unsigned int    fba;            /* 0x00D0 */
  61        unsigned char   res14[0xc];
  62        unsigned int    fpa;            /* 0x00E0 */
  63        unsigned char   res15[0xc];
  64        unsigned int    fsa;            /* 0x00F0 */
  65        unsigned char   res16[0x3c];
  66        unsigned int    sync_mode;      /* 0x0130 */
  67        unsigned char   res17[0xc];
  68        unsigned int    trans_spare;    /* 0x0140 */
  69        unsigned char   res18[0x3c];
  70        unsigned int    err_page_addr;  /* 0x0180 */
  71        unsigned char   res19[0x1c];
  72        unsigned int    int_pin_en;     /* 0x01A0 */
  73        unsigned char   res20[0x1c];
  74        unsigned int    acc_clock;      /* 0x01C0 */
  75        unsigned char   res21[0x1c];
  76        unsigned int    err_blk_addr;   /* 0x01E0 */
  77        unsigned char   res22[0xc];
  78        unsigned int    flash_ver_id;   /* 0x01F0 */
  79        unsigned char   res23[0x6c];
  80        unsigned int    watchdog_cnt_low;       /* 0x0260 */
  81        unsigned char   res24[0xc];
  82        unsigned int    watchdog_cnt_hi;        /* 0x0270 */
  83        unsigned char   res25[0xc];
  84        unsigned int    sync_write;     /* 0x0280 */
  85        unsigned char   res26[0x1c];
  86        unsigned int    cold_reset;     /* 0x02A0 */
  87        unsigned char   res27[0xc];
  88        unsigned int    ddp_device;     /* 0x02B0 */
  89        unsigned char   res28[0xc];
  90        unsigned int    multi_plane;    /* 0x02C0 */
  91        unsigned char   res29[0x1c];
  92        unsigned int    trans_mode;     /* 0x02E0 */
  93        unsigned char   res30[0x1c];
  94        unsigned int    ecc_err_stat2;  /* 0x0300 */
  95        unsigned char   res31[0xc];
  96        unsigned int    ecc_err_stat3;  /* 0x0310 */
  97        unsigned char   res32[0xc];
  98        unsigned int    ecc_err_stat4;  /* 0x0320 */
  99        unsigned char   res33[0x1c];
 100        unsigned int    dev_page_size;  /* 0x0340 */
 101        unsigned char   res34[0x4c];
 102        unsigned int    int_mon_status; /* 0x0390 */
 103};
 104#endif
 105
 106#define ONENAND_MEM_RESET_HOT   0x3
 107#define ONENAND_MEM_RESET_COLD  0x2
 108#define ONENAND_MEM_RESET_WARM  0x1
 109
 110#define INT_ERR_ALL     0x3fff
 111#define CACHE_OP_ERR    (1 << 13)
 112#define RST_CMP         (1 << 12)
 113#define RDY_ACT         (1 << 11)
 114#define INT_ACT         (1 << 10)
 115#define UNSUP_CMD       (1 << 9)
 116#define LOCKED_BLK      (1 << 8)
 117#define BLK_RW_CMP      (1 << 7)
 118#define ERS_CMP         (1 << 6)
 119#define PGM_CMP         (1 << 5)
 120#define LOAD_CMP        (1 << 4)
 121#define ERS_FAIL        (1 << 3)
 122#define PGM_FAIL        (1 << 2)
 123#define INT_TO          (1 << 1)
 124#define LD_FAIL_ECC_ERR (1 << 0)
 125
 126#define TSRF            (1 << 0)
 127
 128/* common initialize function */
 129extern void s3c_onenand_init(struct mtd_info *);
 130extern int s5pc110_chip_probe(struct mtd_info *);
 131extern int s5pc210_chip_probe(struct mtd_info *);
 132
 133#endif
 134