1/* 2 * Copyright (C) 2003 Arabella Software Ltd. 3 * Yuli Barcohen <yuli@arabellasw.com> 4 * 5 * Serial Presence Detect (SPD) EEPROM format according to the 6 * Intel's PC SDRAM Serial Presence Detect (SPD) Specification, 7 * revision 1.2B, November 1999 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, but 15 * WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 22 */ 23 24#ifndef _SPD_H_ 25#define _SPD_H_ 26 27typedef struct spd_eeprom_s { 28 unsigned char info_size; /* 0 # bytes written into serial memory */ 29 unsigned char chip_size; /* 1 Total # bytes of SPD memory device */ 30 unsigned char mem_type; /* 2 Fundamental memory type */ 31 unsigned char nrow_addr; /* 3 # of Row Addresses on this assembly */ 32 unsigned char ncol_addr; /* 4 # of Column Addrs on this assembly */ 33 unsigned char nrows; /* 5 # of Module Rows on this assembly */ 34 unsigned char dataw_lsb; /* 6 Data Width of this assembly */ 35 unsigned char dataw_msb; /* 7 ... Data Width continuation */ 36 unsigned char voltage; /* 8 Voltage intf std of this assembly */ 37 unsigned char clk_cycle; /* 9 SDRAM Cycle time at CL=X */ 38 unsigned char clk_access; /* 10 SDRAM Access from Clock at CL=X */ 39 unsigned char config; /* 11 DIMM Configuration type */ 40 unsigned char refresh; /* 12 Refresh Rate/Type */ 41 unsigned char primw; /* 13 Primary SDRAM Width */ 42 unsigned char ecw; /* 14 Error Checking SDRAM width */ 43 unsigned char min_delay; /* 15 for Back to Back Random Address */ 44 unsigned char burstl; /* 16 Burst Lengths Supported */ 45 unsigned char nbanks; /* 17 # of Banks on Each SDRAM Device */ 46 unsigned char cas_lat; /* 18 CAS# Latencies Supported */ 47 unsigned char cs_lat; /* 19 CS# Latency */ 48 unsigned char write_lat; /* 20 Write Latency (aka Write Recovery) */ 49 unsigned char mod_attr; /* 21 SDRAM Module Attributes */ 50 unsigned char dev_attr; /* 22 SDRAM Device Attributes */ 51 unsigned char clk_cycle2; /* 23 Min SDRAM Cycle time at CL=X-1 */ 52 unsigned char clk_access2; /* 24 SDRAM Access from Clock at CL=X-1 */ 53 unsigned char clk_cycle3; /* 25 Min SDRAM Cycle time at CL=X-2 */ 54 unsigned char clk_access3; /* 26 Max Access from Clock at CL=X-2 */ 55 unsigned char trp; /* 27 Min Row Precharge Time (tRP)*/ 56 unsigned char trrd; /* 28 Min Row Active to Row Active (tRRD) */ 57 unsigned char trcd; /* 29 Min RAS to CAS Delay (tRCD) */ 58 unsigned char tras; /* 30 Minimum RAS Pulse Width (tRAS) */ 59 unsigned char row_dens; /* 31 Density of each row on module */ 60 unsigned char ca_setup; /* 32 Cmd + Addr signal input setup time */ 61 unsigned char ca_hold; /* 33 Cmd and Addr signal input hold time */ 62 unsigned char data_setup; /* 34 Data signal input setup time */ 63 unsigned char data_hold; /* 35 Data signal input hold time */ 64 unsigned char twr; /* 36 Write Recovery time tWR */ 65 unsigned char twtr; /* 37 Int write to read delay tWTR */ 66 unsigned char trtp; /* 38 Int read to precharge delay tRTP */ 67 unsigned char mem_probe; /* 39 Mem analysis probe characteristics */ 68 unsigned char trctrfc_ext; /* 40 Extensions to trc and trfc */ 69 unsigned char trc; /* 41 Min Active to Auto refresh time tRC */ 70 unsigned char trfc; /* 42 Min Auto to Active period tRFC */ 71 unsigned char tckmax; /* 43 Max device cycle time tCKmax */ 72 unsigned char tdqsq; /* 44 Max DQS to DQ skew */ 73 unsigned char tqhs; /* 45 Max Read DataHold skew tQHS */ 74 unsigned char pll_relock; /* 46 PLL Relock time */ 75 unsigned char res[15]; /* 47-xx IDD in SPD and Reserved space */ 76 unsigned char spd_rev; /* 62 SPD Data Revision Code */ 77 unsigned char cksum; /* 63 Checksum for bytes 0-62 */ 78 unsigned char mid[8]; /* 64 Mfr's JEDEC ID code per JEP-108E */ 79 unsigned char mloc; /* 72 Manufacturing Location */ 80 unsigned char mpart[18]; /* 73 Manufacturer's Part Number */ 81 unsigned char rev[2]; /* 91 Revision Code */ 82 unsigned char mdate[2]; /* 93 Manufacturing Date */ 83 unsigned char sernum[4]; /* 95 Assembly Serial Number */ 84 unsigned char mspec[27]; /* 99 Manufacturer Specific Data */ 85 86 /* 87 * Open for Customer Use starting with byte 128. 88 */ 89 unsigned char freq; /* 128 Intel spec: frequency */ 90 unsigned char intel_cas; /* 129 Intel spec: CAS# Latency support */ 91} spd_eeprom_t; 92 93 94/* 95 * Byte 2 Fundamental Memory Types. 96 */ 97#define SPD_MEMTYPE_FPM (0x01) 98#define SPD_MEMTYPE_EDO (0x02) 99#define SPD_MEMTYPE_PIPE_NIBBLE (0x03) 100#define SPD_MEMTYPE_SDRAM (0x04) 101#define SPD_MEMTYPE_ROM (0x05) 102#define SPD_MEMTYPE_SGRAM (0x06) 103#define SPD_MEMTYPE_DDR (0x07) 104#define SPD_MEMTYPE_DDR2 (0x08) 105 106#endif /* _SPD_H_ */ 107