LXR uboot/arch/arm/cpu/arm1136/mx35/iomux.c

   1/*
   2 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
   3 *
   4 * See file CREDITS for list of people who contributed to this
   5 * project.
   6 *
   7 * This program is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU General Public License as
   9 * published by the Free Software Foundation; either version 2 of
  10 * the License, or (at your option) any later version.
  11 *
  12 * This program is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 * GNU General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU General Public License
  18 * along with this program; if not, write to the Free Software
  19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20 * MA 02111-1307 USA
  21 */
  22
  23#include <common.h>
  24#include <asm/io.h>
  25#include <asm/arch/imx-regs.h>
  26#include <asm/arch/mx35_pins.h>
  27#include <asm/arch/iomux.h>
  28
  29/*
  30 * IOMUX register (base) addresses
  31 */
  32enum iomux_reg_addr {
  33        IOMUXGPR = IOMUXC_BASE_ADDR,                    /* General purpose */
  34        IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR + 4,         /* MUX control */
  35        IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + 0x324,     /* last MUX control */
  36        IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + 0x328,     /* Pad control */
  37        IOMUXSW_PAD_END = IOMUXC_BASE_ADDR + 0x794,     /* last Pad control */
  38        IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR + 0x7AC,   /* input select */
  39        IOMUXSW_INPUT_END = IOMUXC_BASE_ADDR + 0x9F4,   /* last input select */
  40};
  41
  42#define MUX_PIN_NUM_MAX         \
  43                (((IOMUXSW_PAD_END - IOMUXSW_PAD_CTL) >> 2) + 1)
  44#define MUX_INPUT_NUM_MUX       \
  45                (((IOMUXSW_INPUT_END - IOMUXSW_INPUT_CTL) >> 2) + 1)
  46
  47/*
  48 * Request ownership for an IO pin. This function has to be the first one
  49 * being called before that pin is used.
  50 */
  51void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
  52{
  53        u32 mux_reg = PIN_TO_IOMUX_MUX(pin);
  54
  55        if (mux_reg != NON_MUX_I) {
  56                mux_reg += IOMUXGPR;
  57                writel(cfg, mux_reg);
  58        }
  59}
  60
  61/*
  62 * Release ownership for an IO pin
  63 */
  64void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
  65{
  66}
  67
  68/*
  69 * This function configures the pad value for a IOMUX pin.
  70 *
  71 * @param  pin     a pin number as defined in iomux_pin_name_t
  72 * @param  config  the ORed value of elements defined in iomux_pad_config_t
  73 */
  74void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config)
  75{
  76        u32 pad_reg = IOMUXGPR + PIN_TO_IOMUX_PAD(pin);
  77
  78        writel(config, pad_reg);
  79}
  80
  81/*
  82 * This function enables/disables the general purpose function for a particular
  83 * signal.
  84 *
  85 * @param  gp   one signal as defined in iomux_gp_func_t
  86 * @param  en   enable/disable
  87 */
  88void mxc_iomux_set_gpr(iomux_gp_func_t gp, int en)
  89{
  90        u32 l;
  91
  92        l = readl(IOMUXGPR);
  93        if (en)
  94                l |= gp;
  95        else
  96                l &= ~gp;
  97
  98        writel(l, IOMUXGPR);
  99}
 100
 101/*
 102 * This function configures input path.
 103 *
 104 * @param input index of input select register as defined in
 105 *                      iomux_input_select_t
 106 * @param config the binary value of elements defined in
 107 *                      iomux_input_config_t
 108 */
 109void mxc_iomux_set_input(iomux_input_select_t input, u32 config)
 110{
 111        u32 reg = IOMUXSW_INPUT_CTL + (input << 2);
 112
 113        writel(config, reg);
 114}
 115