1/* 2 * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> 3 * 4 * (C) Copyright 2009 5 * Marvell Semiconductor <www.marvell.com> 6 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 24 * MA 02110-1301 USA 25 */ 26 27#include <config.h> 28#include "asm/arch/orion5x.h" 29 30/* 31 * Configuration values for SDRAM access setup 32 */ 33 34#define SDRAM_CONFIG 0x3148400 35#define SDRAM_MODE 0x62 36#define SDRAM_CONTROL 0x4041000 37#define SDRAM_TIME_CTRL_LOW 0x11602220 38#define SDRAM_TIME_CTRL_HI 0x40c 39#define SDRAM_OPEN_PAGE_EN 0x0 40/* DDR 1 2x 32M NANYA NT5DS16M16CS-6K ==> 64MB */ 41#define SDRAM_BANK0_SIZE 0x3ff0001 42#define SDRAM_ADDR_CTRL 0x10 43 44#define SDRAM_OP_NOP 0x05 45#define SDRAM_OP_SETMODE 0x03 46 47#define SDRAM_PAD_CTRL_WR_EN 0x80000000 48#define SDRAM_PAD_CTRL_TUNE_EN 0x00010000 49#define SDRAM_PAD_CTRL_DRVN_MASK 0x0000003f 50#define SDRAM_PAD_CTRL_DRVP_MASK 0x00000fc0 51 52/* 53 * For Guideline MEM-3 - Drive Strength value 54 */ 55 56#define DDR1_PAD_STRENGTH_DEFAULT 0x00001000 57#define SDRAM_PAD_CTRL_DRV_STR_MASK 0x00003000 58 59/* 60 * For Guideline MEM-4 - DQS Reference Delay Tuning 61 */ 62 63#define MSAR_ARMDDRCLCK_MASK 0x000000f0 64#define MSAR_ARMDDRCLCK_H_MASK 0x00000100 65 66#define MSAR_ARMDDRCLCK_333_167 0x00000000 67#define MSAR_ARMDDRCLCK_500_167 0x00000030 68#define MSAR_ARMDDRCLCK_667_167 0x00000060 69#define MSAR_ARMDDRCLCK_400_200_1 0x000001E0 70#define MSAR_ARMDDRCLCK_400_200 0x00000010 71#define MSAR_ARMDDRCLCK_600_200 0x00000050 72#define MSAR_ARMDDRCLCK_800_200 0x00000070 73 74#define FTDLL_DDR1_166MHZ 0x0047F001 75 76#define FTDLL_DDR1_200MHZ 0x0044D001 77 78/* 79 * Low-level init happens right after start.S has switched to SVC32, 80 * flushed and disabled caches and disabled MMU. We're still running 81 * from the boot chip select, so the first thing we should do is set 82 * up RAM for us to relocate into. 83 */ 84 85.globl lowlevel_init 86 87lowlevel_init: 88 89 /* Use 'r4 as the base for internal register accesses */ 90 ldr r4, =ORION5X_REGS_PHY_BASE 91 92 /* move internal registers from the default 0xD0000000 93 * to their intended location, defined by SoC */ 94 ldr r3, =0xD0000000 95 add r3, r3, #0x20000 96 str r4, [r3, #0x80] 97 98 /* Use R3 as the base for DRAM registers */ 99 add r3, r4, #0x01000 100 101 /*DDR SDRAM Initialization Control */ 102 ldr r6, =0x00000001 103 str r6, [r3, #0x480] 104 105 /* Use R3 as the base for PCI registers */ 106 add r3, r4, #0x31000 107 108 /* Disable arbiter */ 109 ldr r6, =0x00000030 110 str r6, [r3, #0xd00] 111 112 /* Use R3 as the base for DRAM registers */ 113 add r3, r4, #0x01000 114 115 /* set all dram windows to 0 */ 116 mov r6, #0 117 str r6, [r3, #0x504] 118 str r6, [r3, #0x50C] 119 str r6, [r3, #0x514] 120 str r6, [r3, #0x51C] 121 122 /* 1) Configure SDRAM */ 123 ldr r6, =SDRAM_CONFIG 124 str r6, [r3, #0x400] 125 126 /* 2) Set SDRAM Control reg */ 127 ldr r6, =SDRAM_CONTROL 128 str r6, [r3, #0x404] 129 130 /* 3) Write SDRAM address control register */ 131 ldr r6, =SDRAM_ADDR_CTRL 132 str r6, [r3, #0x410] 133 134 /* 4) Write SDRAM bank 0 size register */ 135 ldr r6, =SDRAM_BANK0_SIZE 136 str r6, [r3, #0x504] 137 /* keep other banks disabled */ 138 139 /* 5) Write SDRAM open pages control register */ 140 ldr r6, =SDRAM_OPEN_PAGE_EN 141 str r6, [r3, #0x414] 142 143 /* 6) Write SDRAM timing Low register */ 144 ldr r6, =SDRAM_TIME_CTRL_LOW 145 str r6, [r3, #0x408] 146 147 /* 7) Write SDRAM timing High register */ 148 ldr r6, =SDRAM_TIME_CTRL_HI 149 str r6, [r3, #0x40C] 150 151 /* 8) Write SDRAM mode register */ 152 /* The CPU must not attempt to change the SDRAM Mode register setting */ 153 /* prior to DRAM controller completion of the DRAM initialization */ 154 /* sequence. To guarantee this restriction, it is recommended that */ 155 /* the CPU sets the SDRAM Operation register to NOP command, performs */ 156 /* read polling until the register is back in Normal operation value, */ 157 /* and then sets SDRAM Mode register to its new value. */ 158 159 /* 8.1 write 'nop' to SDRAM operation */ 160 ldr r6, =SDRAM_OP_NOP 161 str r6, [r3, #0x418] 162 163 /* 8.2 poll SDRAM operation until back in 'normal' mode. */ 1641: 165 ldr r6, [r3, #0x418] 166 cmp r6, #0 167 bne 1b 168 169 /* 8.3 Now its safe to write new value to SDRAM Mode register */ 170 ldr r6, =SDRAM_MODE 171 str r6, [r3, #0x41C] 172 173 /* 8.4 Set new mode */ 174 ldr r6, =SDRAM_OP_SETMODE 175 str r6, [r3, #0x418] 176 177 /* 8.5 poll SDRAM operation until back in 'normal' mode. */ 1782: 179 ldr r6, [r3, #0x418] 180 cmp r6, #0 181 bne 2b 182 183 /* DDR SDRAM Address/Control Pads Calibration */ 184 ldr r6, [r3, #0x4C0] 185 186 /* Set Bit [31] to make the register writable */ 187 orr r6, r6, #SDRAM_PAD_CTRL_WR_EN 188 str r6, [r3, #0x4C0] 189 190 bic r6, r6, #SDRAM_PAD_CTRL_WR_EN 191 bic r6, r6, #SDRAM_PAD_CTRL_TUNE_EN 192 bic r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK 193 bic r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK 194 195 /* Get the final N locked value of driving strength [22:17] */ 196 mov r1, r6 197 mov r1, r1, LSL #9 198 mov r1, r1, LSR #26 /* r1[5:0]<DrvN> = r3[22:17]<LockN> */ 199 orr r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> = r1[5:0]<DrvN> */ 200 201 /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */ 202 orr r6, r6, r1 203 str r6, [r3, #0x4C0] 204 205 /* DDR SDRAM Data Pads Calibration */ 206 ldr r6, [r3, #0x4C4] 207 208 /* Set Bit [31] to make the register writable */ 209 orr r6, r6, #SDRAM_PAD_CTRL_WR_EN 210 str r6, [r3, #0x4C4] 211 212 bic r6, r6, #SDRAM_PAD_CTRL_WR_EN 213 bic r6, r6, #SDRAM_PAD_CTRL_TUNE_EN 214 bic r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK 215 bic r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK 216 217 /* Get the final N locked value of driving strength [22:17] */ 218 mov r1, r6 219 mov r1, r1, LSL #9 220 mov r1, r1, LSR #26 221 orr r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN> */ 222 223 /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */ 224 orr r6, r6, r1 225 226 str r6, [r3, #0x4C4] 227 228 /* Implement Guideline (GL# MEM-3) Drive Strength Value */ 229 /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */ 230 231 ldr r1, =DDR1_PAD_STRENGTH_DEFAULT 232 233 /* Enable writes to DDR SDRAM Addr/Ctrl Pads Calibration register */ 234 ldr r6, [r3, #0x4C0] 235 orr r6, r6, #SDRAM_PAD_CTRL_WR_EN 236 str r6, [r3, #0x4C0] 237 238 /* Correct strength and disable writes again */ 239 bic r6, r6, #SDRAM_PAD_CTRL_WR_EN 240 bic r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASK 241 orr r6, r6, r1 242 str r6, [r3, #0x4C0] 243 244 /* Enable writes to DDR SDRAM Data Pads Calibration register */ 245 ldr r6, [r3, #0x4C4] 246 orr r6, r6, #SDRAM_PAD_CTRL_WR_EN 247 str r6, [r3, #0x4C4] 248 249 /* Correct strength and disable writes again */ 250 bic r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASK 251 bic r6, r6, #SDRAM_PAD_CTRL_WR_EN 252 orr r6, r6, r1 253 str r6, [r3, #0x4C4] 254 255 /* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */ 256 /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */ 257 258 /* Get the "sample on reset" register for the DDR frequancy */ 259 ldr r3, =0x10000 260 ldr r6, [r3, #0x010] 261 ldr r1, =MSAR_ARMDDRCLCK_MASK 262 and r1, r6, r1 263 264 ldr r6, =FTDLL_DDR1_166MHZ 265 cmp r1, #MSAR_ARMDDRCLCK_333_167 266 beq 3f 267 cmp r1, #MSAR_ARMDDRCLCK_500_167 268 beq 3f 269 cmp r1, #MSAR_ARMDDRCLCK_667_167 270 beq 3f 271 272 ldr r6, =FTDLL_DDR1_200MHZ 273 cmp r1, #MSAR_ARMDDRCLCK_400_200_1 274 beq 3f 275 cmp r1, #MSAR_ARMDDRCLCK_400_200 276 beq 3f 277 cmp r1, #MSAR_ARMDDRCLCK_600_200 278 beq 3f 279 cmp r1, #MSAR_ARMDDRCLCK_800_200 280 beq 3f 281 282 ldr r6, =0 283 2843: 285 /* Use R3 as the base for DRAM registers */ 286 add r3, r4, #0x01000 287 288 ldr r2, [r3, #0x484] 289 orr r2, r2, r6 290 str r2, [r3, #0x484] 291 292 /* Return to U-boot via saved link register */ 293 mov pc, lr 294