1/* 2 * Copyright (C) 2012 Samsung Electronics 3 * Donghwa Lee <dh09.lee@samsung.com> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24#include <common.h> 25#include <asm/io.h> 26#include <asm/arch/system.h> 27 28static void exynos5_set_usbhost_mode(unsigned int mode) 29{ 30 struct exynos5_sysreg *sysreg = 31 (struct exynos5_sysreg *)samsung_get_base_sysreg(); 32 33 /* Setting USB20PHY_CONFIG register to USB 2.0 HOST link */ 34 if (mode == USB20_PHY_CFG_HOST_LINK_EN) { 35 setbits_le32(&sysreg->usb20phy_cfg, 36 USB20_PHY_CFG_HOST_LINK_EN); 37 } else { 38 clrbits_le32(&sysreg->usb20phy_cfg, 39 USB20_PHY_CFG_HOST_LINK_EN); 40 } 41} 42 43void set_usbhost_mode(unsigned int mode) 44{ 45 if (cpu_is_exynos5()) 46 exynos5_set_usbhost_mode(mode); 47} 48 49static void exynos4_set_system_display(void) 50{ 51 struct exynos4_sysreg *sysreg = 52 (struct exynos4_sysreg *)samsung_get_base_sysreg(); 53 unsigned int cfg = 0; 54 55 /* 56 * system register path set 57 * 0: MIE/MDNIE 58 * 1: FIMD Bypass 59 */ 60 cfg = readl(&sysreg->display_ctrl); 61 cfg |= (1 << 1); 62 writel(cfg, &sysreg->display_ctrl); 63} 64 65static void exynos5_set_system_display(void) 66{ 67 struct exynos5_sysreg *sysreg = 68 (struct exynos5_sysreg *)samsung_get_base_sysreg(); 69 unsigned int cfg = 0; 70 71 /* 72 * system register path set 73 * 0: MIE/MDNIE 74 * 1: FIMD Bypass 75 */ 76 cfg = readl(&sysreg->disp1blk_cfg); 77 cfg |= (1 << 15); 78 writel(cfg, &sysreg->disp1blk_cfg); 79} 80 81void set_system_display_ctrl(void) 82{ 83 if (cpu_is_exynos4()) 84 exynos4_set_system_display(); 85 else 86 exynos5_set_system_display(); 87} 88