LXR uboot/arch/arm/cpu/armv7/omap3/mem.c

   1/*
   2 * (C) Copyright 2008
   3 * Texas Instruments, <www.ti.com>
   4 *
   5 * Author :
   6 *     Manikandan Pillai <mani.pillai@ti.com>
   7 *
   8 * Initial Code from:
   9 *     Richard Woodruff <r-woodruff2@ti.com>
  10 *     Syed Mohammed Khasim <khasim@ti.com>
  11 *
  12 * This program is free software; you can redistribute it and/or
  13 * modify it under the terms of the GNU General Public License as
  14 * published by the Free Software Foundation; either version 2 of
  15 * the License, or (at your option) any later version.
  16 *
  17 * This program is distributed in the hope that it will be useful,
  18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20 * GNU General Public License for more details.
  21 *
  22 * You should have received a copy of the GNU General Public License
  23 * along with this program; if not, write to the Free Software
  24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25 * MA 02111-1307 USA
  26 */
  27
  28#include <common.h>
  29#include <asm/io.h>
  30#include <asm/arch/mem.h>
  31#include <asm/arch/sys_proto.h>
  32#include <command.h>
  33
  34struct gpmc *gpmc_cfg;
  35
  36#if defined(CONFIG_CMD_NAND)
  37static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
  38        M_NAND_GPMC_CONFIG1,
  39        M_NAND_GPMC_CONFIG2,
  40        M_NAND_GPMC_CONFIG3,
  41        M_NAND_GPMC_CONFIG4,
  42        M_NAND_GPMC_CONFIG5,
  43        M_NAND_GPMC_CONFIG6, 0
  44};
  45
  46#if defined(CONFIG_ENV_IS_IN_NAND)
  47#define GPMC_CS 0
  48#else
  49#define GPMC_CS 1
  50#endif
  51
  52#endif
  53
  54#if defined(CONFIG_CMD_ONENAND)
  55static const u32 gpmc_onenand[GPMC_MAX_REG] = {
  56        ONENAND_GPMC_CONFIG1,
  57        ONENAND_GPMC_CONFIG2,
  58        ONENAND_GPMC_CONFIG3,
  59        ONENAND_GPMC_CONFIG4,
  60        ONENAND_GPMC_CONFIG5,
  61        ONENAND_GPMC_CONFIG6, 0
  62};
  63
  64#if defined(CONFIG_ENV_IS_IN_ONENAND)
  65#define GPMC_CS 0
  66#else
  67#define GPMC_CS 1
  68#endif
  69
  70#endif
  71
  72/********************************************************
  73 *  mem_ok() - test used to see if timings are correct
  74 *             for a part. Helps in guessing which part
  75 *             we are currently using.
  76 *******************************************************/
  77u32 mem_ok(u32 cs)
  78{
  79        u32 val1, val2, addr;
  80        u32 pattern = 0x12345678;
  81
  82        addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs);
  83
  84        writel(0x0, addr + 0x400);      /* clear pos A */
  85        writel(pattern, addr);          /* pattern to pos B */
  86        writel(0x0, addr + 4);          /* remove pattern off the bus */
  87        val1 = readl(addr + 0x400);     /* get pos A value */
  88        val2 = readl(addr);             /* get val2 */
  89        writel(0x0, addr + 0x400);      /* clear pos A */
  90
  91        if ((val1 != 0) || (val2 != pattern))   /* see if pos A val changed */
  92                return 0;
  93        else
  94                return 1;
  95}
  96
  97void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
  98                        u32 size)
  99{
 100        writel(0, &cs->config7);
 101        sdelay(1000);
 102        /* Delay for settling */
 103        writel(gpmc_config[0], &cs->config1);
 104        writel(gpmc_config[1], &cs->config2);
 105        writel(gpmc_config[2], &cs->config3);
 106        writel(gpmc_config[3], &cs->config4);
 107        writel(gpmc_config[4], &cs->config5);
 108        writel(gpmc_config[5], &cs->config6);
 109
 110        /*
 111         * Enable the config.  size is the CS size and goes in
 112         * bits 11:8.  We set bit 6 to enable this CS and the base
 113         * address goes into bits 5:0.
 114         */
 115         writel((size << 8) | (GPMC_CS_ENABLE << 6) |
 116                                 ((base >> 24) & GPMC_BASEADDR_MASK),
 117                                 &cs->config7);
 118        sdelay(2000);
 119}
 120
 121/*****************************************************
 122 * gpmc_init(): init gpmc bus
 123 * Init GPMC for x16, MuxMode (SDRAM in x32).
 124 * This code can only be executed from SRAM or SDRAM.
 125 *****************************************************/
 126void gpmc_init(void)
 127{
 128        /* putting a blanket check on GPMC based on ZeBu for now */
 129        gpmc_cfg = (struct gpmc *)GPMC_BASE;
 130#if defined(CONFIG_CMD_NAND) || defined(CONFIG_CMD_ONENAND)
 131        const u32 *gpmc_config = NULL;
 132        u32 base = 0;
 133        u32 size = 0;
 134#endif
 135        u32 config = 0;
 136
 137        /* global settings */
 138        writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */
 139        writel(0, &gpmc_cfg->timeout_control);/* timeout disable */
 140
 141        config = readl(&gpmc_cfg->config);
 142        config &= (~0xf00);
 143        writel(config, &gpmc_cfg->config);
 144
 145        /*
 146         * Disable the GPMC0 config set by ROM code
 147         * It conflicts with our MPDB (both at 0x08000000)
 148         */
 149        writel(0, &gpmc_cfg->cs[0].config7);
 150        sdelay(1000);
 151
 152#if defined(CONFIG_CMD_NAND)    /* CS 0 */
 153        gpmc_config = gpmc_m_nand;
 154
 155        base = PISMO1_NAND_BASE;
 156        size = PISMO1_NAND_SIZE;
 157        enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
 158#endif
 159
 160#if defined(CONFIG_CMD_ONENAND)
 161        gpmc_config = gpmc_onenand;
 162        base = PISMO1_ONEN_BASE;
 163        size = PISMO1_ONEN_SIZE;
 164        enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
 165#endif
 166}
 167