LXR uboot/arch/arm/cpu/lh7a40x/start.S

   1/*
   2 *  armboot - Startup Code for ARM920 CPU-core
   3 *
   4 *  Copyright (c) 2001  Marius Gröger <mag@sysgo.de>
   5 *  Copyright (c) 2002  Alex Züpke <azu@sysgo.de>
   6 *  Copyright (c) 2002  Gary Jennejohn <garyj@denx.de>
   7 *
   8 * See file CREDITS for list of people who contributed to this
   9 * project.
  10 *
  11 * This program is free software; you can redistribute it and/or
  12 * modify it under the terms of the GNU General Public License as
  13 * published by the Free Software Foundation; either version 2 of
  14 * the License, or (at your option) any later version.
  15 *
  16 * This program is distributed in the hope that it will be useful,
  17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 * GNU General Public License for more details.
  20 *
  21 * You should have received a copy of the GNU General Public License
  22 * along with this program; if not, write to the Free Software
  23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24 * MA 02111-1307 USA
  25 */
  26
  27#include <asm-offsets.h>
  28#include <config.h>
  29#include <version.h>
  30
  31/*
  32 *************************************************************************
  33 *
  34 * Jump vector table as in table 3.1 in [1]
  35 *
  36 *************************************************************************
  37 */
  38
  39
  40.globl _start
  41_start: b       reset
  42        ldr     pc, _undefined_instruction
  43        ldr     pc, _software_interrupt
  44        ldr     pc, _prefetch_abort
  45        ldr     pc, _data_abort
  46        ldr     pc, _not_used
  47        ldr     pc, _irq
  48        ldr     pc, _fiq
  49
  50_undefined_instruction: .word undefined_instruction
  51_software_interrupt:    .word software_interrupt
  52_prefetch_abort:        .word prefetch_abort
  53_data_abort:            .word data_abort
  54_not_used:              .word not_used
  55_irq:                   .word irq
  56_fiq:                   .word fiq
  57
  58        .balignl 16,0xdeadbeef
  59
  60
  61/*
  62 *************************************************************************
  63 *
  64 * Startup Code (reset vector)
  65 *
  66 * do important init only if we don't start from memory!
  67 * relocate armboot to ram
  68 * setup stack
  69 * jump to second stage
  70 *
  71 *************************************************************************
  72 */
  73
  74.globl _TEXT_BASE
  75_TEXT_BASE:
  76        .word   CONFIG_SYS_TEXT_BASE
  77
  78/*
  79 * These are defined in the board-specific linker script.
  80 * Subtracting _start from them lets the linker put their
  81 * relative position in the executable instead of leaving
  82 * them null.
  83 */
  84.globl _bss_start_ofs
  85_bss_start_ofs:
  86        .word __bss_start - _start
  87
  88.globl _bss_end_ofs
  89_bss_end_ofs:
  90        .word __bss_end__ - _start
  91
  92.globl _end_ofs
  93_end_ofs:
  94        .word _end - _start
  95
  96#ifdef CONFIG_USE_IRQ
  97/* IRQ stack memory (calculated at run-time) */
  98.globl IRQ_STACK_START
  99IRQ_STACK_START:
 100        .word   0x0badc0de
 101
 102/* IRQ stack memory (calculated at run-time) */
 103.globl FIQ_STACK_START
 104FIQ_STACK_START:
 105        .word 0x0badc0de
 106#endif
 107
 108/* IRQ stack memory (calculated at run-time) + 8 bytes */
 109.globl IRQ_STACK_START_IN
 110IRQ_STACK_START_IN:
 111        .word   0x0badc0de
 112
 113/*
 114 * the actual reset code
 115 */
 116
 117reset:
 118        /*
 119         * set the cpu to SVC32 mode
 120         */
 121        mrs     r0,cpsr
 122        bic     r0,r0,#0x1f
 123        orr     r0,r0,#0xd3
 124        msr     cpsr,r0
 125
 126#define pWDTCTL         0x80001400  /* Watchdog Timer control register */
 127#define pINTENC         0x8000050C  /* Interrupt-Controller enable clear register */
 128#define pCLKSET         0x80000420  /* clock divisor register */
 129
 130        /* disable watchdog, set watchdog control register to
 131         * all zeros (default reset)
 132         */
 133        ldr     r0, =pWDTCTL
 134        mov     r1, #0x0
 135        str     r1, [r0]
 136
 137        /*
 138         * mask all IRQs by setting all bits in the INTENC register (default)
 139         */
 140        mov     r1, #0xffffffff
 141        ldr     r0, =pINTENC
 142        str     r1, [r0]
 143
 144        /* FCLK:HCLK:PCLK = 1:2:2 */
 145        /* default FCLK is 200 MHz, using 14.7456 MHz fin */
 146        ldr     r0, =pCLKSET
 147        ldr r1, =0x0004ee39
 148@       ldr r1, =0x0005ee39     @ 1: 2: 4
 149        str     r1, [r0]
 150
 151        /*
 152         * we do sys-critical inits only at reboot,
 153         * not when booting from ram!
 154         */
 155#ifndef CONFIG_SKIP_LOWLEVEL_INIT
 156        bl      cpu_init_crit
 157#endif
 158
 159/* Set stackpointer in internal RAM to call board_init_f */
 160call_board_init_f:
 161        ldr     sp, =(CONFIG_SYS_INIT_SP_ADDR)
 162        bic     sp, sp, #7 /* 8-byte alignment for ABI compliance */
 163        ldr     r0,=0x00000000
 164        bl      board_init_f
 165
 166/*------------------------------------------------------------------------------*/
 167
 168/*
 169 * void relocate_code (addr_sp, gd, addr_moni)
 170 *
 171 * This "function" does not return, instead it continues in RAM
 172 * after relocating the monitor code.
 173 *
 174 */
 175        .globl  relocate_code
 176relocate_code:
 177        mov     r4, r0  /* save addr_sp */
 178        mov     r5, r1  /* save addr of gd */
 179        mov     r6, r2  /* save addr of destination */
 180
 181        /* Set up the stack                                                 */
 182stack_setup:
 183        mov     sp, r4
 184
 185        adr     r0, _start
 186        cmp     r0, r6
 187        moveq   r9, #0          /* no relocation. relocation offset(r9) = 0 */
 188        beq     clear_bss               /* skip relocation */
 189        mov     r1, r6                  /* r1 <- scratch for copy_loop */
 190        ldr     r3, _bss_start_ofs
 191        add     r2, r0, r3              /* r2 <- source end address         */
 192
 193copy_loop:
 194        ldmia   r0!, {r9-r10}           /* copy from source address [r0]    */
 195        stmia   r1!, {r9-r10}           /* copy to   target address [r1]    */
 196        cmp     r0, r2                  /* until source end address [r2]    */
 197        blo     copy_loop
 198
 199#ifndef CONFIG_SPL_BUILD
 200        /*
 201         * fix .rel.dyn relocations
 202         */
 203        ldr     r0, _TEXT_BASE          /* r0 <- Text base */
 204        sub     r9, r6, r0              /* r9 <- relocation offset */
 205        ldr     r10, _dynsym_start_ofs  /* r10 <- sym table ofs */
 206        add     r10, r10, r0            /* r10 <- sym table in FLASH */
 207        ldr     r2, _rel_dyn_start_ofs  /* r2 <- rel dyn start ofs */
 208        add     r2, r2, r0              /* r2 <- rel dyn start in FLASH */
 209        ldr     r3, _rel_dyn_end_ofs    /* r3 <- rel dyn end ofs */
 210        add     r3, r3, r0              /* r3 <- rel dyn end in FLASH */
 211fixloop:
 212        ldr     r0, [r2]                /* r0 <- location to fix up, IN FLASH! */
 213        add     r0, r0, r9              /* r0 <- location to fix up in RAM */
 214        ldr     r1, [r2, #4]
 215        and     r7, r1, #0xff
 216        cmp     r7, #23                 /* relative fixup? */
 217        beq     fixrel
 218        cmp     r7, #2                  /* absolute fixup? */
 219        beq     fixabs
 220        /* ignore unknown type of fixup */
 221        b       fixnext
 222fixabs:
 223        /* absolute fix: set location to (offset) symbol value */
 224        mov     r1, r1, LSR #4          /* r1 <- symbol index in .dynsym */
 225        add     r1, r10, r1             /* r1 <- address of symbol in table */
 226        ldr     r1, [r1, #4]            /* r1 <- symbol value */
 227        add     r1, r1, r9              /* r1 <- relocated sym addr */
 228        b       fixnext
 229fixrel:
 230        /* relative fix: increase location by offset */
 231        ldr     r1, [r0]
 232        add     r1, r1, r9
 233fixnext:
 234        str     r1, [r0]
 235        add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
 236        cmp     r2, r3
 237        blo     fixloop
 238#endif
 239
 240clear_bss:
 241#ifndef CONFIG_SPL_BUILD
 242        ldr     r0, _bss_start_ofs
 243        ldr     r1, _bss_end_ofs
 244        mov     r4, r6                  /* reloc addr */
 245        add     r0, r0, r4
 246        add     r1, r1, r4
 247        mov     r2, #0x00000000         /* clear                            */
 248
 249clbss_l:cmp     r0, r1                  /* clear loop... */
 250        bhs     clbss_e                 /* if reached end of bss, exit */
 251        str     r2, [r0]
 252        add     r0, r0, #4
 253        b       clbss_l
 254clbss_e:
 255#endif
 256
 257/*
 258 * We are done. Do not return, instead branch to second part of board
 259 * initialization, now running from RAM.
 260 */
 261        ldr     r0, _board_init_r_ofs
 262        adr     r1, _start
 263        add     lr, r0, r1
 264        add     lr, lr, r9
 265        /* setup parameters for board_init_r */
 266        mov     r0, r5          /* gd_t */
 267        mov     r1, r6          /* dest_addr */
 268        /* jump to it ... */
 269        mov     pc, lr
 270
 271_board_init_r_ofs:
 272        .word board_init_r - _start
 273
 274_rel_dyn_start_ofs:
 275        .word __rel_dyn_start - _start
 276_rel_dyn_end_ofs:
 277        .word __rel_dyn_end - _start
 278_dynsym_start_ofs:
 279        .word __dynsym_start - _start
 280
 281/*
 282 *************************************************************************
 283 *
 284 * CPU_init_critical registers
 285 *
 286 * setup important registers
 287 * setup memory timing
 288 *
 289 *************************************************************************
 290 */
 291
 292
 293cpu_init_crit:
 294        /*
 295         * flush v4 I/D caches
 296         */
 297        mov     r0, #0
 298        mcr     p15, 0, r0, c7, c7, 0   /* flush v3/v4 cache */
 299        mcr     p15, 0, r0, c8, c7, 0   /* flush v4 TLB */
 300
 301        /*
 302         * disable MMU stuff and caches
 303         */
 304        mrc     p15, 0, r0, c1, c0, 0
 305        bic     r0, r0, #0x00002300     @ clear bits 13, 9:8 (--V- --RS)
 306        bic     r0, r0, #0x00000087     @ clear bits 7, 2:0 (B--- -CAM)
 307        orr     r0, r0, #0x00000002     @ set bit 2 (A) Align
 308        orr     r0, r0, #0x00001000     @ set bit 12 (I) I-Cache
 309        orr     r0, r0, #0x40000000     @ set bit 30 (nF) notFastBus
 310        mcr     p15, 0, r0, c1, c0, 0
 311
 312
 313        /*
 314         * before relocating, we have to setup RAM timing
 315         * because memory timing is board-dependend, you will
 316         * find a lowlevel_init.S in your board directory.
 317         */
 318        mov     ip, lr
 319        bl      lowlevel_init
 320        mov     lr, ip
 321
 322        mov     pc, lr
 323
 324
 325/*
 326 *************************************************************************
 327 *
 328 * Interrupt handling
 329 *
 330 *************************************************************************
 331 */
 332
 333@
 334@ IRQ stack frame.
 335@
 336#define S_FRAME_SIZE    72
 337
 338#define S_OLD_R0        68
 339#define S_PSR           64
 340#define S_PC            60
 341#define S_LR            56
 342#define S_SP            52
 343
 344#define S_IP            48
 345#define S_FP            44
 346#define S_R10           40
 347#define S_R9            36
 348#define S_R8            32
 349#define S_R7            28
 350#define S_R6            24
 351#define S_R5            20
 352#define S_R4            16
 353#define S_R3            12
 354#define S_R2            8
 355#define S_R1            4
 356#define S_R0            0
 357
 358#define MODE_SVC 0x13
 359#define I_BIT    0x80
 360
 361/*
 362 * use bad_save_user_regs for abort/prefetch/undef/swi ...
 363 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
 364 */
 365
 366        .macro  bad_save_user_regs
 367        sub     sp, sp, #S_FRAME_SIZE
 368        stmia   sp, {r0 - r12}                  @ Calling r0-r12
 369        ldr     r2, IRQ_STACK_START_IN
 370        ldmia   r2, {r2 - r3}                   @ get pc, cpsr
 371        add     r0, sp, #S_FRAME_SIZE           @ restore sp_SVC
 372
 373        add     r5, sp, #S_SP
 374        mov     r1, lr
 375        stmia   r5, {r0 - r3}                   @ save sp_SVC, lr_SVC, pc, cpsr
 376        mov     r0, sp
 377        .endm
 378
 379        .macro  irq_save_user_regs
 380        sub     sp, sp, #S_FRAME_SIZE
 381        stmia   sp, {r0 - r12}                  @ Calling r0-r12
 382        add     r8, sp, #S_PC
 383        stmdb   r8, {sp, lr}^                   @ Calling SP, LR
 384        str     lr, [r8, #0]                    @ Save calling PC
 385        mrs     r6, spsr
 386        str     r6, [r8, #4]                    @ Save CPSR
 387        str     r0, [r8, #8]                    @ Save OLD_R0
 388        mov     r0, sp
 389        .endm
 390
 391        .macro  irq_restore_user_regs
 392        ldmia   sp, {r0 - lr}^                  @ Calling r0 - lr
 393        mov     r0, r0
 394        ldr     lr, [sp, #S_PC]                 @ Get PC
 395        add     sp, sp, #S_FRAME_SIZE
 396        subs    pc, lr, #4                      @ return & move spsr_svc into cpsr
 397        .endm
 398
 399        .macro get_bad_stack
 400        ldr     r13, IRQ_STACK_START_IN         @ setup our mode stack
 401
 402        str     lr, [r13]                       @ save caller lr / spsr
 403        mrs     lr, spsr
 404        str     lr, [r13, #4]
 405
 406        mov     r13, #MODE_SVC                  @ prepare SVC-Mode
 407        @ msr   spsr_c, r13
 408        msr     spsr, r13
 409        mov     lr, pc
 410        movs    pc, lr
 411        .endm
 412
 413        .macro get_irq_stack                    @ setup IRQ stack
 414        ldr     sp, IRQ_STACK_START
 415        .endm
 416
 417        .macro get_fiq_stack                    @ setup FIQ stack
 418        ldr     sp, FIQ_STACK_START
 419        .endm
 420
 421/*
 422 * exception handlers
 423 */
 424        .align  5
 425undefined_instruction:
 426        get_bad_stack
 427        bad_save_user_regs
 428        bl      do_undefined_instruction
 429
 430        .align  5
 431software_interrupt:
 432        get_bad_stack
 433        bad_save_user_regs
 434        bl      do_software_interrupt
 435
 436        .align  5
 437prefetch_abort:
 438        get_bad_stack
 439        bad_save_user_regs
 440        bl      do_prefetch_abort
 441
 442        .align  5
 443data_abort:
 444        get_bad_stack
 445        bad_save_user_regs
 446        bl      do_data_abort
 447
 448        .align  5
 449not_used:
 450        get_bad_stack
 451        bad_save_user_regs
 452        bl      do_not_used
 453
 454#ifdef CONFIG_USE_IRQ
 455
 456        .align  5
 457irq:
 458        get_irq_stack
 459        irq_save_user_regs
 460        bl      do_irq
 461        irq_restore_user_regs
 462
 463        .align  5
 464fiq:
 465        get_fiq_stack
 466        /* someone ought to write a more effiction fiq_save_user_regs */
 467        irq_save_user_regs
 468        bl      do_fiq
 469        irq_restore_user_regs
 470
 471#else
 472
 473        .align  5
 474irq:
 475        get_bad_stack
 476        bad_save_user_regs
 477        bl      do_irq
 478
 479        .align  5
 480fiq:
 481        get_bad_stack
 482        bad_save_user_regs
 483        bl      do_fiq
 484
 485#endif
 486
 487        .align  5
 488.globl reset_cpu
 489reset_cpu:
 490        bl      disable_interrupts
 491
 492        /* Disable watchdog */
 493        ldr     r1, =pWDTCTL
 494        mov     r3, #0
 495        str     r3, [r1]
 496
 497        /* reset counter */
 498        ldr     r3, =0x00001984
 499        str     r3, [r1, #4]
 500
 501        /* Enable the watchdog */
 502        mov     r3, #1
 503        str     r3, [r1]
 504
 505_loop_forever:
 506        b       _loop_forever
 507