1/* 2 * (C) Copyright 2010 3 * Texas Instruments, <www.ti.com> 4 * 5 * Authors: 6 * Aneesh V <aneesh@ti.com> 7 * Sricharan R <r.sricharan@ti.com> 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28#ifndef _OMAP5_H_ 29#define _OMAP5_H_ 30 31#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 32#include <asm/types.h> 33#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ 34 35/* 36 * L4 Peripherals - L4 Wakeup and L4 Core now 37 */ 38#define OMAP54XX_L4_CORE_BASE 0x4A000000 39#define OMAP54XX_L4_WKUP_BASE 0x4Ae00000 40#define OMAP54XX_L4_PER_BASE 0x48000000 41 42#define OMAP54XX_DRAM_ADDR_SPACE_START 0x80000000 43#define OMAP54XX_DRAM_ADDR_SPACE_END 0xFFFFFFFF 44#define DRAM_ADDR_SPACE_START OMAP54XX_DRAM_ADDR_SPACE_START 45#define DRAM_ADDR_SPACE_END OMAP54XX_DRAM_ADDR_SPACE_END 46 47/* CONTROL */ 48#define CTRL_BASE (OMAP54XX_L4_CORE_BASE + 0x2000) 49#define CONTROL_PADCONF_CORE (CTRL_BASE + 0x0800) 50#define CONTROL_PADCONF_WKUP (OMAP54XX_L4_WKUP_BASE + 0xc800) 51 52/* LPDDR2 IO regs. To be verified */ 53#define LPDDR2_IO_REGS_BASE 0x4A100638 54 55/* CONTROL_ID_CODE */ 56#define CONTROL_ID_CODE (CTRL_BASE + 0x204) 57 58/* To be verified */ 59#define OMAP5430_CONTROL_ID_CODE_ES1_0 0x0B94202F 60#define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F 61 62/* STD_FUSE_PROD_ID_1 */ 63#define STD_FUSE_PROD_ID_1 (CTRL_BASE + 0x218) 64#define PROD_ID_1_SILICON_TYPE_SHIFT 16 65#define PROD_ID_1_SILICON_TYPE_MASK (3 << 16) 66 67/* UART */ 68#define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000) 69#define UART2_BASE (OMAP54XX_L4_PER_BASE + 0x6c000) 70#define UART3_BASE (OMAP54XX_L4_PER_BASE + 0x20000) 71 72/* General Purpose Timers */ 73#define GPT1_BASE (OMAP54XX_L4_WKUP_BASE + 0x18000) 74#define GPT2_BASE (OMAP54XX_L4_PER_BASE + 0x32000) 75#define GPT3_BASE (OMAP54XX_L4_PER_BASE + 0x34000) 76 77/* Watchdog Timer2 - MPU watchdog */ 78#define WDT2_BASE (OMAP54XX_L4_WKUP_BASE + 0x14000) 79 80/* 32KTIMER */ 81#define SYNC_32KTIMER_BASE (OMAP54XX_L4_WKUP_BASE + 0x4000) 82 83/* GPMC */ 84#define OMAP54XX_GPMC_BASE 0x50000000 85 86/* SYSTEM CONTROL MODULE */ 87#define SYSCTRL_GENERAL_CORE_BASE 0x4A002000 88 89/* 90 * Hardware Register Details 91 */ 92 93/* Watchdog Timer */ 94#define WD_UNLOCK1 0xAAAA 95#define WD_UNLOCK2 0x5555 96 97/* GP Timer */ 98#define TCLR_ST (0x1 << 0) 99#define TCLR_AR (0x1 << 1) 100#define TCLR_PRE (0x1 << 5) 101 102/* Control Module */ 103#define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5) 104#define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f 105#define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110 106#define CONTROL_EFUSE_2_OVERRIDE 0x00084000 107 108/* LPDDR2 IO regs */ 109#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C 110#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E 111#define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C 112#define LPDDR2IO_GR10_WD_MASK (3 << 17) 113#define CONTROL_LPDDR2IO_3_VAL 0xA0888C00 114 115/* CONTROL_EFUSE_2 */ 116#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000 117 118#define SDCARD_PWRDNZ (1 << 26) 119#define SDCARD_BIAS_HIZ_MODE (1 << 25) 120#define SDCARD_BIAS_PWRDNZ (1 << 22) 121#define SDCARD_PBIASLITE_VMODE (1 << 21) 122 123#ifndef __ASSEMBLY__ 124 125struct s32ktimer { 126 unsigned char res[0x10]; 127 unsigned int s32k_cr; /* 0x10 */ 128}; 129 130#define DEVICE_TYPE_SHIFT 0x6 131#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT) 132#define DEVICE_GP 0x3 133 134struct omap_sys_ctrl_regs { 135 u32 pad0[77]; /* 0x4A002000 */ 136 u32 control_status; /* 0x4A002134 */ 137 u32 pad1[794]; /* 0x4A002138 */ 138 u32 control_paconf_global; /* 0x4A002DA0 */ 139 u32 control_paconf_mode; /* 0x4A002DA4 */ 140 u32 control_smart1io_padconf_0; /* 0x4A002DA8 */ 141 u32 control_smart1io_padconf_1; /* 0x4A002DAC */ 142 u32 control_smart1io_padconf_2; /* 0x4A002DB0 */ 143 u32 control_smart2io_padconf_0; /* 0x4A002DB4 */ 144 u32 control_smart2io_padconf_1; /* 0x4A002DB8 */ 145 u32 control_smart2io_padconf_2; /* 0x4A002DBC */ 146 u32 control_smart3io_padconf_0; /* 0x4A002DC0 */ 147 u32 control_smart3io_padconf_1; /* 0x4A002DC4 */ 148 u32 pad2[14]; 149 u32 control_pbias; /* 0x4A002E00 */ 150 u32 control_i2c_0; /* 0x4A002E04 */ 151 u32 control_camera_rx; /* 0x4A002E08 */ 152 u32 control_hdmi_tx_phy; /* 0x4A002E0C */ 153 u32 control_uniportm; /* 0x4A002E10 */ 154 u32 control_dsiphy; /* 0x4A002E14 */ 155 u32 control_mcbsplp; /* 0x4A002E18 */ 156 u32 control_usb2phycore; /* 0x4A002E1C */ 157 u32 control_hdmi_1; /*0x4A002E20*/ 158 u32 control_hsi; /*0x4A002E24*/ 159 u32 pad3[2]; 160 u32 control_ddr3ch1_0; /*0x4A002E30*/ 161 u32 control_ddr3ch2_0; /*0x4A002E34*/ 162 u32 control_ddrch1_0; /*0x4A002E38*/ 163 u32 control_ddrch1_1; /*0x4A002E3C*/ 164 u32 control_ddrch2_0; /*0x4A002E40*/ 165 u32 control_ddrch2_1; /*0x4A002E44*/ 166 u32 control_lpddr2ch1_0; /*0x4A002E48*/ 167 u32 control_lpddr2ch1_1; /*0x4A002E4C*/ 168 u32 control_ddrio_0; /*0x4A002E50*/ 169 u32 control_ddrio_1; /*0x4A002E54*/ 170 u32 control_ddrio_2; /*0x4A002E58*/ 171 u32 control_hyst_1; /*0x4A002E5C*/ 172 u32 control_usbb_hsic_control; /*0x4A002E60*/ 173 u32 control_c2c; /*0x4A002E64*/ 174 u32 control_core_control_spare_rw; /*0x4A002E68*/ 175 u32 control_core_control_spare_r; /*0x4A002E6C*/ 176 u32 control_core_control_spare_r_c0; /*0x4A002E70*/ 177 u32 control_srcomp_north_side; /*0x4A002E74*/ 178 u32 control_srcomp_south_side; /*0x4A002E78*/ 179 u32 control_srcomp_east_side; /*0x4A002E7C*/ 180 u32 control_srcomp_west_side; /*0x4A002E80*/ 181 u32 control_srcomp_code_latch; /*0x4A002E84*/ 182 u32 pad4[3679394]; 183 u32 control_port_emif1_sdram_config; /*0x4AE0C110*/ 184 u32 control_port_emif1_lpddr2_nvm_config; /*0x4AE0C114*/ 185 u32 control_port_emif2_sdram_config; /*0x4AE0C118*/ 186 u32 pad5[10]; 187 u32 control_emif1_sdram_config_ext; /* 0x4AE0C144 */ 188 u32 control_emif2_sdram_config_ext; /* 0x4AE0C148 */ 189 u32 pad6[789]; 190 u32 control_smart1nopmio_padconf_0; /* 0x4AE0CDA0 */ 191 u32 control_smart1nopmio_padconf_1; /* 0x4AE0CDA4 */ 192 u32 control_padconf_mode; /* 0x4AE0CDA8 */ 193 u32 control_xtal_oscillator; /* 0x4AE0CDAC */ 194 u32 control_i2c_2; /* 0x4AE0CDB0 */ 195 u32 control_ckobuffer; /* 0x4AE0CDB4 */ 196 u32 control_wkup_control_spare_rw; /* 0x4AE0CDB8 */ 197 u32 control_wkup_control_spare_r; /* 0x4AE0CDBC */ 198 u32 control_wkup_control_spare_r_c0; /* 0x4AE0CDC0 */ 199 u32 control_srcomp_east_side_wkup; /* 0x4AE0CDC4 */ 200 u32 control_efuse_1; /* 0x4AE0CDC8 */ 201 u32 control_efuse_2; /* 0x4AE0CDCC */ 202 u32 control_efuse_3; /* 0x4AE0CDD0 */ 203 u32 control_efuse_4; /* 0x4AE0CDD4 */ 204 u32 control_efuse_5; /* 0x4AE0CDD8 */ 205 u32 control_efuse_6; /* 0x4AE0CDDC */ 206 u32 control_efuse_7; /* 0x4AE0CDE0 */ 207 u32 control_efuse_8; /* 0x4AE0CDE4 */ 208 u32 control_efuse_9; /* 0x4AE0CDE8 */ 209 u32 control_efuse_10; /* 0x4AE0CDEC */ 210 u32 control_efuse_11; /* 0x4AE0CDF0 */ 211 u32 control_efuse_12; /* 0x4AE0CDF4 */ 212 u32 control_efuse_13; /* 0x4AE0CDF8 */ 213}; 214 215/* Output impedance control */ 216#define ds_120_ohm 0x0 217#define ds_60_ohm 0x1 218#define ds_45_ohm 0x2 219#define ds_30_ohm 0x3 220#define ds_mask 0x3 221 222/* Slew rate control */ 223#define sc_slow 0x0 224#define sc_medium 0x1 225#define sc_fast 0x2 226#define sc_na 0x3 227#define sc_mask 0x3 228 229/* Target capacitance control */ 230#define lb_5_12_pf 0x0 231#define lb_12_25_pf 0x1 232#define lb_25_50_pf 0x2 233#define lb_50_80_pf 0x3 234#define lb_mask 0x3 235 236#define usb_i_mask 0x7 237 238#define DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN 0x80828082 239#define DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN 0x82828200 240#define DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL 0x8421 241#define DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL 0x8421084 242#define DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL 0x8421000 243 244#define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL 0x7C7C7C6C 245#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL 0x64646464 246#define DDR_IO_0_VREF_CELLS_DDR3_VALUE 0xBAE8C631 247#define DDR_IO_1_VREF_CELLS_DDR3_VALUE 0xBC6318DC 248#define DDR_IO_2_VREF_CELLS_DDR3_VALUE 0x0 249 250#define EFUSE_1 0x45145100 251#define EFUSE_2 0x45145100 252#define EFUSE_3 0x45145100 253#define EFUSE_4 0x45145100 254#endif /* __ASSEMBLY__ */ 255 256/* 257 * Non-secure SRAM Addresses 258 * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE 259 * at 0x40304000(EMU base) so that our code works for both EMU and GP 260 */ 261#define NON_SECURE_SRAM_START 0x40300000 262#define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */ 263/* base address for indirect vectors (internal boot mode) */ 264#define SRAM_ROM_VECT_BASE 0x4031F000 265 266#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START 267/* 268 * SRAM scratch space entries 269 */ 270#define OMAP5_SRAM_SCRATCH_OMAP5_REV SRAM_SCRATCH_SPACE_ADDR 271#define OMAP5_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4) 272#define OMAP5_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC) 273#define OMAP5_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10) 274#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x14) 275 276/* Silicon revisions */ 277#define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF 278#define OMAP4430_ES1_0 0x44300100 279#define OMAP4430_ES2_0 0x44300200 280#define OMAP4430_ES2_1 0x44300210 281#define OMAP4430_ES2_2 0x44300220 282#define OMAP4430_ES2_3 0x44300230 283#define OMAP4460_ES1_0 0x44600100 284#define OMAP4460_ES1_1 0x44600110 285 286/* ROM code defines */ 287/* Boot device */ 288#define BOOT_DEVICE_MASK 0xFF 289#define BOOT_DEVICE_OFFSET 0x8 290#define DEV_DESC_PTR_OFFSET 0x4 291#define DEV_DATA_PTR_OFFSET 0x18 292#define BOOT_MODE_OFFSET 0x8 293#define RESET_REASON_OFFSET 0x9 294#define CH_FLAGS_OFFSET 0xA 295 296#define CH_FLAGS_CHSETTINGS (0x1 << 0) 297#define CH_FLAGS_CHRAM (0x1 << 1) 298#define CH_FLAGS_CHFLASH (0x1 << 2) 299#define CH_FLAGS_CHMMCSD (0x1 << 3) 300 301#ifndef __ASSEMBLY__ 302struct omap_boot_parameters { 303 char *boot_message; 304 unsigned int mem_boot_descriptor; 305 unsigned char omap_bootdevice; 306 unsigned char reset_reason; 307 unsigned char ch_flags; 308}; 309#endif /* __ASSEMBLY__ */ 310#endif 311