LXR uboot/arch/blackfin/include/asm/mach-bf506/anomaly.h

   1/*
   2 * DO NOT EDIT THIS FILE
   3 * This file is under version control at
   4 *   svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
   5 * and can be replaced with that version at any time
   6 * DO NOT EDIT THIS FILE
   7 *
   8 * Copyright 2004-2011 Analog Devices Inc.
   9 * Licensed under the ADI BSD license.
  10 *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
  11 */
  12
  13/* This file should be up to date with:
  14 *  - Revision A, 02/18/2011; ADSP-BF504/BF504F/BF506F Blackfin Processor Anomaly List
  15 */
  16
  17#if __SILICON_REVISION__ < 0
  18# error will not work on BF506 silicon version
  19#endif
  20
  21#ifndef _MACH_ANOMALY_H_
  22#define _MACH_ANOMALY_H_
  23
  24/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
  25#define ANOMALY_05000074 (1)
  26/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
  27#define ANOMALY_05000119 (1)
  28/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
  29#define ANOMALY_05000122 (1)
  30/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
  31#define ANOMALY_05000245 (1)
  32/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
  33#define ANOMALY_05000254 (1)
  34/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
  35#define ANOMALY_05000265 (1)
  36/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
  37#define ANOMALY_05000310 (1)
  38/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
  39#define ANOMALY_05000366 (1)
  40/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
  41#define ANOMALY_05000426 (1)
  42/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
  43#define ANOMALY_05000443 (1)
  44/* UART IrDA Receiver Fails on Extended Bit Pulses */
  45#define ANOMALY_05000447 (1)
  46/* False Hardware Error when RETI Points to Invalid Memory */
  47#define ANOMALY_05000461 (1)
  48/* PLL Latches Incorrect Settings During Reset */
  49#define ANOMALY_05000469 (1)
  50/* Incorrect Default MSEL Value in PLL_CTL */
  51#define ANOMALY_05000472 (1)
  52/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
  53#define ANOMALY_05000473 (1)
  54/* SPORT0 Data Transmit Error in Multi-Channel Mode with Internal Clock */
  55#define ANOMALY_05000476 (1)
  56/* TESTSET Instruction Cannot Be Interrupted */
  57#define ANOMALY_05000477 (1)
  58/* Disabling ACM During an Ongoing Transfer Can Lead to Undefined ACM Behavior */
  59#define ANOMALY_05000478 (1)
  60/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
  61#define ANOMALY_05000481 (1)
  62/* TWI Vbus Minimum Specification Can Be Violated under Certain Conditions */
  63#define ANOMALY_05000486 (1)
  64/* SPI Master Boot Can Fail Under Certain Conditions */
  65#define ANOMALY_05000490 (1)
  66/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
  67#define ANOMALY_05000491 (1)
  68/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
  69#define ANOMALY_05000494 (1)
  70/* Maximum Idd-deepsleep Specifications Can Be Exceeded under Certain Conditions */
  71#define ANOMALY_05000495 (1)
  72/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
  73#define ANOMALY_05000498 (1)
  74/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
  75#define ANOMALY_05000501 (1)
  76
  77/* Anomalies that don't exist on this proc */
  78#define ANOMALY_05000099 (0)
  79#define ANOMALY_05000120 (0)
  80#define ANOMALY_05000125 (0)
  81#define ANOMALY_05000149 (0)
  82#define ANOMALY_05000158 (0)
  83#define ANOMALY_05000171 (0)
  84#define ANOMALY_05000179 (0)
  85#define ANOMALY_05000182 (0)
  86#define ANOMALY_05000183 (0)
  87#define ANOMALY_05000189 (0)
  88#define ANOMALY_05000198 (0)
  89#define ANOMALY_05000202 (0)
  90#define ANOMALY_05000215 (0)
  91#define ANOMALY_05000219 (0)
  92#define ANOMALY_05000220 (0)
  93#define ANOMALY_05000227 (0)
  94#define ANOMALY_05000230 (0)
  95#define ANOMALY_05000231 (0)
  96#define ANOMALY_05000233 (0)
  97#define ANOMALY_05000234 (0)
  98#define ANOMALY_05000242 (0)
  99#define ANOMALY_05000244 (0)
 100#define ANOMALY_05000248 (0)
 101#define ANOMALY_05000250 (0)
 102#define ANOMALY_05000257 (0)
 103#define ANOMALY_05000261 (0)
 104#define ANOMALY_05000263 (0)
 105#define ANOMALY_05000266 (0)
 106#define ANOMALY_05000273 (0)
 107#define ANOMALY_05000274 (0)
 108#define ANOMALY_05000278 (0)
 109#define ANOMALY_05000281 (0)
 110#define ANOMALY_05000283 (0)
 111#define ANOMALY_05000285 (0)
 112#define ANOMALY_05000287 (0)
 113#define ANOMALY_05000301 (0)
 114#define ANOMALY_05000305 (0)
 115#define ANOMALY_05000307 (0)
 116#define ANOMALY_05000311 (0)
 117#define ANOMALY_05000312 (0)
 118#define ANOMALY_05000315 (0)
 119#define ANOMALY_05000323 (0)
 120#define ANOMALY_05000353 (0)
 121#define ANOMALY_05000357 (0)
 122#define ANOMALY_05000362 (1)
 123#define ANOMALY_05000363 (0)
 124#define ANOMALY_05000364 (0)
 125#define ANOMALY_05000371 (0)
 126#define ANOMALY_05000380 (0)
 127#define ANOMALY_05000383 (0)
 128#define ANOMALY_05000386 (0)
 129#define ANOMALY_05000389 (0)
 130#define ANOMALY_05000400 (0)
 131#define ANOMALY_05000402 (0)
 132#define ANOMALY_05000412 (0)
 133#define ANOMALY_05000432 (0)
 134#define ANOMALY_05000440 (0)
 135#define ANOMALY_05000448 (0)
 136#define ANOMALY_05000456 (0)
 137#define ANOMALY_05000450 (0)
 138#define ANOMALY_05000465 (0)
 139#define ANOMALY_05000467 (0)
 140#define ANOMALY_05000474 (0)
 141#define ANOMALY_05000475 (0)
 142#define ANOMALY_05000480 (0)
 143#define ANOMALY_05000485 (0)
 144
 145#endif
 146