1/* 2 * MCF547x_8x Internal Memory Map 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26#ifndef __IMMAP_547x_8x__ 27#define __IMMAP_547x_8x__ 28 29#define MMAP_SIU (CONFIG_SYS_MBAR + 0x00000000) 30#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000100) 31#define MMAP_XARB (CONFIG_SYS_MBAR + 0x00000240) 32#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000500) 33#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000700) 34#define MMAP_GPTMR (CONFIG_SYS_MBAR + 0x00000800) 35#define MMAP_SLT0 (CONFIG_SYS_MBAR + 0x00000900) 36#define MMAP_SLT1 (CONFIG_SYS_MBAR + 0x00000910) 37#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00000A00) 38#define MMAP_PCI (CONFIG_SYS_MBAR + 0x00000B00) 39#define MMAP_PCIARB (CONFIG_SYS_MBAR + 0x00000C00) 40#define MMAP_EXTDMA (CONFIG_SYS_MBAR + 0x00000D00) 41#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00000F00) 42#define MMAP_CTM (CONFIG_SYS_MBAR + 0x00007F00) 43#define MMAP_MCDMA (CONFIG_SYS_MBAR + 0x00008000) 44#define MMAP_SCPCI (CONFIG_SYS_MBAR + 0x00008400) 45#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00008600) 46#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00008700) 47#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00008800) 48#define MMAP_UART3 (CONFIG_SYS_MBAR + 0x00008900) 49#define MMAP_DSPI (CONFIG_SYS_MBAR + 0x00008A00) 50#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00008F00) 51#define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00009000) 52#define MMAP_FEC1 (CONFIG_SYS_MBAR + 0x00009800) 53#define MMAP_CAN0 (CONFIG_SYS_MBAR + 0x0000A000) 54#define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x0000A800) 55#define MMAP_USBD (CONFIG_SYS_MBAR + 0x0000B000) 56#define MMAP_SRAM (CONFIG_SYS_MBAR + 0x00010000) 57#define MMAP_SRAMCFG (CONFIG_SYS_MBAR + 0x0001FF00) 58#define MMAP_SEC (CONFIG_SYS_MBAR + 0x00020000) 59 60#include <asm/coldfire/dspi.h> 61#include <asm/coldfire/eport.h> 62#include <asm/coldfire/flexbus.h> 63#include <asm/coldfire/flexcan.h> 64#include <asm/coldfire/intctrl.h> 65 66typedef struct siu { 67 u32 mbar; /* 0x00 */ 68 u32 drv; /* 0x04 */ 69 u32 rsvd1[2]; /* 0x08 - 0x1F */ 70 u32 sbcr; /* 0x10 */ 71 u32 rsvd2[3]; /* 0x14 - 0x1F */ 72 u32 cs0cfg; /* 0x20 */ 73 u32 cs1cfg; /* 0x24 */ 74 u32 cs2cfg; /* 0x28 */ 75 u32 cs3cfg; /* 0x2C */ 76 u32 rsvd3[2]; /* 0x30 - 0x37 */ 77 u32 secsacr; /* 0x38 */ 78 u32 rsvd4[2]; /* 0x3C - 0x43 */ 79 u32 rsr; /* 0x44 */ 80 u32 rsvd5[2]; /* 0x48 - 0x4F */ 81 u32 jtagid; /* 0x50 */ 82} siu_t; 83 84typedef struct sdram { 85 u32 mode; /* 0x00 */ 86 u32 ctrl; /* 0x04 */ 87 u32 cfg1; /* 0x08 */ 88 u32 cfg2; /* 0x0c */ 89} sdram_t; 90 91typedef struct xlb_arb { 92 u32 cfg; /* 0x240 */ 93 u32 ver; /* 0x244 */ 94 u32 sr; /* 0x248 */ 95 u32 imr; /* 0x24c */ 96 u32 adrcap; /* 0x250 */ 97 u32 sigcap; /* 0x254 */ 98 u32 adrto; /* 0x258 */ 99 u32 datto; /* 0x25c */ 100 u32 busto; /* 0x260 */ 101 u32 prien; /* 0x264 */ 102 u32 pri; /* 0x268 */ 103} xlbarb_t; 104 105typedef struct gptmr { 106 u8 ocpw; 107 u8 octict; 108 u8 ctrl; 109 u8 mode; 110 111 u16 pre; /* Prescale */ 112 u16 cnt; 113 114 u16 pwmwidth; 115 u8 pwmop; /* Output Polarity */ 116 u8 pwmld; /* Immediate Update */ 117 118 u16 cap; /* Capture internal counter */ 119 u8 ovfpin; /* Ovf and Pin */ 120 u8 intr; /* Interrupts */ 121} gptmr_t; 122 123typedef struct canex_ctrl { 124 can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */ 125} canex_t; 126 127 128typedef struct slt { 129 u32 tcnt; /* 0x00 */ 130 u32 cr; /* 0x04 */ 131 u32 cnt; /* 0x08 */ 132 u32 sr; /* 0x0C */ 133} slt_t; 134 135typedef struct gpio { 136 /* Port Output Data Registers */ 137 u8 podr_fbctl; /*0x00 */ 138 u8 podr_fbcs; /*0x01 */ 139 u8 podr_dma; /*0x02 */ 140 u8 rsvd1; /*0x03 */ 141 u8 podr_fec0h; /*0x04 */ 142 u8 podr_fec0l; /*0x05 */ 143 u8 podr_fec1h; /*0x06 */ 144 u8 podr_fec1l; /*0x07 */ 145 u8 podr_feci2c; /*0x08 */ 146 u8 podr_pcibg; /*0x09 */ 147 u8 podr_pcibr; /*0x0A */ 148 u8 rsvd2; /*0x0B */ 149 u8 podr_psc3psc2; /*0x0C */ 150 u8 podr_psc1psc0; /*0x0D */ 151 u8 podr_dspi; /*0x0E */ 152 u8 rsvd3; /*0x0F */ 153 154 /* Port Data Direction Registers */ 155 u8 pddr_fbctl; /*0x10 */ 156 u8 pddr_fbcs; /*0x11 */ 157 u8 pddr_dma; /*0x12 */ 158 u8 rsvd4; /*0x13 */ 159 u8 pddr_fec0h; /*0x14 */ 160 u8 pddr_fec0l; /*0x15 */ 161 u8 pddr_fec1h; /*0x16 */ 162 u8 pddr_fec1l; /*0x17 */ 163 u8 pddr_feci2c; /*0x18 */ 164 u8 pddr_pcibg; /*0x19 */ 165 u8 pddr_pcibr; /*0x1A */ 166 u8 rsvd5; /*0x1B */ 167 u8 pddr_psc3psc2; /*0x1C */ 168 u8 pddr_psc1psc0; /*0x1D */ 169 u8 pddr_dspi; /*0x1E */ 170 u8 rsvd6; /*0x1F */ 171 172 /* Port Pin Data/Set Data Registers */ 173 u8 ppdsdr_fbctl; /*0x20 */ 174 u8 ppdsdr_fbcs; /*0x21 */ 175 u8 ppdsdr_dma; /*0x22 */ 176 u8 rsvd7; /*0x23 */ 177 u8 ppdsdr_fec0h; /*0x24 */ 178 u8 ppdsdr_fec0l; /*0x25 */ 179 u8 ppdsdr_fec1h; /*0x26 */ 180 u8 ppdsdr_fec1l; /*0x27 */ 181 u8 ppdsdr_feci2c; /*0x28 */ 182 u8 ppdsdr_pcibg; /*0x29 */ 183 u8 ppdsdr_pcibr; /*0x2A */ 184 u8 rsvd8; /*0x2B */ 185 u8 ppdsdr_psc3psc2; /*0x2C */ 186 u8 ppdsdr_psc1psc0; /*0x2D */ 187 u8 ppdsdr_dspi; /*0x2E */ 188 u8 rsvd9; /*0x2F */ 189 190 /* Port Clear Output Data Registers */ 191 u8 pclrr_fbctl; /*0x30 */ 192 u8 pclrr_fbcs; /*0x31 */ 193 u8 pclrr_dma; /*0x32 */ 194 u8 rsvd10; /*0x33 */ 195 u8 pclrr_fec0h; /*0x34 */ 196 u8 pclrr_fec0l; /*0x35 */ 197 u8 pclrr_fec1h; /*0x36 */ 198 u8 pclrr_fec1l; /*0x37 */ 199 u8 pclrr_feci2c; /*0x38 */ 200 u8 pclrr_pcibg; /*0x39 */ 201 u8 pclrr_pcibr; /*0x3A */ 202 u8 rsvd11; /*0x3B */ 203 u8 pclrr_psc3psc2; /*0x3C */ 204 u8 pclrr_psc1psc0; /*0x3D */ 205 u8 pclrr_dspi; /*0x3E */ 206 u8 rsvd12; /*0x3F */ 207 208 /* Pin Assignment Registers */ 209 u16 par_fbctl; /*0x40 */ 210 u8 par_fbcs; /*0x42 */ 211 u8 par_dma; /*0x43 */ 212 u16 par_feci2cirq; /*0x44 */ 213 u16 rsvd13; /*0x46 */ 214 u16 par_pcibg; /*0x48 */ 215 u16 par_pcibr; /*0x4A */ 216 u8 par_psc3; /*0x4C */ 217 u8 par_psc2; /*0x4D */ 218 u8 par_psc1; /*0x4E */ 219 u8 par_psc0; /*0x4F */ 220 u16 par_dspi; /*0x50 */ 221 u8 par_timer; /*0x52 */ 222 u8 rsvd14; /*0x53 */ 223} gpio_t; 224 225typedef struct pci { 226 u32 idr; /* 0x00 Device Id / Vendor Id */ 227 u32 scr; /* 0x04 Status / command */ 228 u32 ccrir; /* 0x08 Class Code / Revision Id */ 229 u32 cr1; /* 0x0c Configuration 1 */ 230 u32 bar0; /* 0x10 Base address register 0 */ 231 u32 bar1; /* 0x14 Base address register 1 */ 232 u32 bar2; /* 0x18 NA */ 233 u32 bar3; /* 0x1c NA */ 234 u32 bar4; /* 0x20 NA */ 235 u32 bar5; /* 0x24 NA */ 236 u32 ccpr; /* 0x28 Cardbus CIS Pointer */ 237 u32 sid; /* 0x2c Subsystem ID / Subsystem Vendor ID */ 238 u32 erbar; /* 0x30 Expansion ROM Base Address */ 239 u32 cpr; /* 0x34 Capabilities Pointer */ 240 u32 rsvd1; /* 0x38 */ 241 u32 cr2; /* 0x3c Configuration 2 */ 242 u32 rsvd2[8]; /* 0x40 - 0x5f */ 243 244 /* General control / status registers */ 245 u32 gscr; /* 0x60 Global Status / Control */ 246 u32 tbatr0a; /* 0x64 Target Base Adr Translation 0 */ 247 u32 tbatr1a; /* 0x68 Target Base Adr Translation 1 */ 248 u32 tcr1; /* 0x6c Target Control 1 Register */ 249 u32 iw0btar; /* 0x70 Initiator Win 0 Base/Translation adr */ 250 u32 iw1btar; /* 0x74 Initiator Win 1 Base/Translation adr */ 251 u32 iw2btar; /* 0x78 NA */ 252 u32 rsvd3; /* 0x7c */ 253 u32 iwcr; /* 0x80 Initiator Window Configuration */ 254 u32 icr; /* 0x84 Initiator Control */ 255 u32 isr; /* 0x88 Initiator Status */ 256 u32 tcr2; /* 0x8c NA */ 257 u32 tbatr0; /* 0x90 NA */ 258 u32 tbatr1; /* 0x94 NA */ 259 u32 tbatr2; /* 0x98 NA */ 260 u32 tbatr3; /* 0x9c NA */ 261 u32 tbatr4; /* 0xa0 NA */ 262 u32 tbatr5; /* 0xa4 NA */ 263 u32 intr; /* 0xa8 NA */ 264 u32 rsvd4[19]; /* 0xac - 0xf7 */ 265 u32 car; /* 0xf8 Configuration Address */ 266} pci_t; 267 268typedef struct pci_arbiter { 269 /* Pci Arbiter Registers */ 270 union { 271 u32 acr; /* Arbiter Control */ 272 u32 asr; /* Arbiter Status */ 273 }; 274} pciarb_t; 275#endif /* __IMMAP_547x_8x__ */ 276