1/* 2 * Copyright 2009-2011 Freescale Semiconductor, Inc. 3 * Dave Liu <daveliu@freescale.com> 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License as 7 * published by the Free Software Foundation; either version 2 of 8 * the License, or (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 18 * MA 02111-1307 USA 19 */ 20 21#ifndef __TGEC_H__ 22#define __TGEC_H__ 23 24#include <phy.h> 25 26struct tgec { 27 /* 10GEC general control and status registers */ 28 u32 tgec_id; /* Controller ID register */ 29 u32 res0; 30 u32 command_config; /* Control and configuration register */ 31 u32 mac_addr_0; /* Lower 32 bits of 48-bit MAC address */ 32 u32 mac_addr_1; /* Upper 16 bits of 48-bit MAC address */ 33 u32 maxfrm; /* Maximum frame length register */ 34 u32 pause_quant; /* Pause quanta register */ 35 u32 res1[4]; 36 u32 hashtable_ctrl; /* Hash table control register */ 37 u32 res2[4]; 38 u32 status; /* MAC status register */ 39 u32 tx_ipg_length; /* Transmitter inter-packet-gap register */ 40 u32 mac_addr_2; /* Lower 32 bits of the 2nd 48-bit MAC addr */ 41 u32 mac_addr_3; /* Upper 16 bits of the 2nd 48-bit MAC addr */ 42 u32 res3[4]; 43 u32 imask; /* Interrupt mask register */ 44 u32 ievent; /* Interrupt event register */ 45 u32 res4[6]; 46 /* 10GEC statistics counter registers */ 47 u32 tx_frame_u; /* Tx frame counter upper */ 48 u32 tx_frame_l; /* Tx frame counter lower */ 49 u32 rx_frame_u; /* Rx frame counter upper */ 50 u32 rx_frame_l; /* Rx frame counter lower */ 51 u32 rx_frame_crc_err_u; /* Rx frame check sequence error upper */ 52 u32 rx_frame_crc_err_l; /* Rx frame check sequence error lower */ 53 u32 rx_align_err_u; /* Rx alignment error upper */ 54 u32 rx_align_err_l; /* Rx alignment error lower */ 55 u32 tx_pause_frame_u; /* Tx valid pause frame upper */ 56 u32 tx_pause_frame_l; /* Tx valid pause frame lower */ 57 u32 rx_pause_frame_u; /* Rx valid pause frame upper */ 58 u32 rx_pause_frame_l; /* Rx valid pause frame upper */ 59 u32 rx_long_err_u; /* Rx too long frame error upper */ 60 u32 rx_long_err_l; /* Rx too long frame error lower */ 61 u32 rx_frame_err_u; /* Rx frame length error upper */ 62 u32 rx_frame_err_l; /* Rx frame length error lower */ 63 u32 tx_vlan_u; /* Tx VLAN frame upper */ 64 u32 tx_vlan_l; /* Tx VLAN frame lower */ 65 u32 rx_vlan_u; /* Rx VLAN frame upper */ 66 u32 rx_vlan_l; /* Rx VLAN frame lower */ 67 u32 tx_oct_u; /* Tx octets upper */ 68 u32 tx_oct_l; /* Tx octets lower */ 69 u32 rx_oct_u; /* Rx octets upper */ 70 u32 rx_oct_l; /* Rx octets lower */ 71 u32 rx_uni_u; /* Rx unicast frame upper */ 72 u32 rx_uni_l; /* Rx unicast frame lower */ 73 u32 rx_multi_u; /* Rx multicast frame upper */ 74 u32 rx_multi_l; /* Rx multicast frame lower */ 75 u32 rx_brd_u; /* Rx broadcast frame upper */ 76 u32 rx_brd_l; /* Rx broadcast frame lower */ 77 u32 tx_frame_err_u; /* Tx frame error upper */ 78 u32 tx_frame_err_l; /* Tx frame error lower */ 79 u32 tx_uni_u; /* Tx unicast frame upper */ 80 u32 tx_uni_l; /* Tx unicast frame lower */ 81 u32 tx_multi_u; /* Tx multicast frame upper */ 82 u32 tx_multi_l; /* Tx multicast frame lower */ 83 u32 tx_brd_u; /* Tx broadcast frame upper */ 84 u32 tx_brd_l; /* Tx broadcast frame lower */ 85 u32 rx_drop_u; /* Rx dropped packets upper */ 86 u32 rx_drop_l; /* Rx dropped packets lower */ 87 u32 rx_eoct_u; /* Rx ethernet octets upper */ 88 u32 rx_eoct_l; /* Rx ethernet octets lower */ 89 u32 rx_pkt_u; /* Rx packets upper */ 90 u32 rx_pkt_l; /* Rx packets lower */ 91 u32 tx_undsz_u; /* Undersized packet upper */ 92 u32 tx_undsz_l; /* Undersized packet lower */ 93 u32 rx_64_u; /* Rx 64 oct packet upper */ 94 u32 rx_64_l; /* Rx 64 oct packet lower */ 95 u32 rx_127_u; /* Rx 65 to 127 oct packet upper */ 96 u32 rx_127_l; /* Rx 65 to 127 oct packet lower */ 97 u32 rx_255_u; /* Rx 128 to 255 oct packet upper */ 98 u32 rx_255_l; /* Rx 128 to 255 oct packet lower */ 99 u32 rx_511_u; /* Rx 256 to 511 oct packet upper */ 100 u32 rx_511_l; /* Rx 256 to 511 oct packet lower */ 101 u32 rx_1023_u; /* Rx 512 to 1023 oct packet upper */ 102 u32 rx_1023_l; /* Rx 512 to 1023 oct packet lower */ 103 u32 rx_1518_u; /* Rx 1024 to 1518 oct packet upper */ 104 u32 rx_1518_l; /* Rx 1024 to 1518 oct packet lower */ 105 u32 rx_1519_u; /* Rx 1519 to max oct packet upper */ 106 u32 rx_1519_l; /* Rx 1519 to max oct packet lower */ 107 u32 tx_oversz_u; /* oversized packet upper */ 108 u32 tx_oversz_l; /* oversized packet lower */ 109 u32 tx_jabber_u; /* Jabber packet upper */ 110 u32 tx_jabber_l; /* Jabber packet lower */ 111 u32 tx_frag_u; /* Fragment packet upper */ 112 u32 tx_frag_l; /* Fragment packet lower */ 113 u32 rx_err_u; /* Rx frame error upper */ 114 u32 rx_err_l; /* Rx frame error lower */ 115 u32 res5[0x39a]; 116}; 117 118/* EC10G_ID - 10-gigabit ethernet MAC controller ID */ 119#define EC10G_ID_VER_MASK 0x0000ff00 120#define EC10G_ID_VER_SHIFT 8 121#define EC10G_ID_REV_MASK 0x000000ff 122 123/* COMMAND_CONFIG - command and configuration register */ 124#define TGEC_CMD_CFG_EN_TIMESTAMP 0x00100000 /* enable IEEE1588 */ 125#define TGEC_CMD_CFG_TX_ADDR_INS_SEL 0x00080000 /* Tx mac addr w/ second */ 126#define TGEC_CMD_CFG_NO_LEN_CHK 0x00020000 /* payload len chk disable */ 127#define TGEC_CMD_CFG_SEND_IDLE 0x00010000 /* send XGMII idle seqs */ 128#define TGEC_CMD_CFG_RX_ER_DISC 0x00004000 /* Rx err frm discard enb */ 129#define TGEC_CMD_CFG_CMD_FRM_EN 0x00002000 /* CMD frame RX enable */ 130#define TGEC_CMD_CFG_STAT_CLR 0x00001000 /* clear stats */ 131#define TGEC_CMD_CFG_TX_ADDR_INS 0x00000200 /* overwrite src MAC addr */ 132#define TGEC_CMD_CFG_PAUSE_IGNORE 0x00000100 /* ignore pause frames */ 133#define TGEC_CMD_CFG_PAUSE_FWD 0x00000080 /* fwd pause frames */ 134#define TGEC_CMD_CFG_CRC_FWD 0x00000040 /* fwd Rx CRC frames */ 135#define TGEC_CMD_CFG_PAD_EN 0x00000020 /* MAC remove Rx padding */ 136#define TGEC_CMD_CFG_PROM_EN 0x00000010 /* promiscuous mode enable */ 137#define TGEC_CMD_CFG_WAN_MODE 0x00000008 /* WAN mode enable */ 138#define TGEC_CMD_CFG_RX_EN 0x00000002 /* MAC Rx path enable */ 139#define TGEC_CMD_CFG_TX_EN 0x00000001 /* MAC Tx path enable */ 140#define TGEC_CMD_CFG_RXTX_EN (TGEC_CMD_CFG_RX_EN | TGEC_CMD_CFG_TX_EN) 141 142/* HASHTABLE_CTRL - Hashtable control register */ 143#define HASHTABLE_CTRL_MCAST_EN 0x00000200 /* enable mulitcast Rx hash */ 144#define HASHTABLE_CTRL_ADDR_MASK 0x000001ff 145 146/* TX_IPG_LENGTH - Transmit inter-packet gap length register */ 147#define TX_IPG_LENGTH_IPG_LEN_MASK 0x000003ff 148 149/* IMASK - interrupt mask register */ 150#define IMASK_MDIO_SCAN_EVENT 0x00010000 /* MDIO scan event mask */ 151#define IMASK_MDIO_CMD_CMPL 0x00008000 /* MDIO cmd completion mask */ 152#define IMASK_REM_FAULT 0x00004000 /* remote fault mask */ 153#define IMASK_LOC_FAULT 0x00002000 /* local fault mask */ 154#define IMASK_TX_ECC_ER 0x00001000 /* Tx frame ECC error mask */ 155#define IMASK_TX_FIFO_UNFL 0x00000800 /* Tx FIFO underflow mask */ 156#define IMASK_TX_ER 0x00000200 /* Tx frame error mask */ 157#define IMASK_RX_FIFO_OVFL 0x00000100 /* Rx FIFO overflow mask */ 158#define IMASK_RX_ECC_ER 0x00000080 /* Rx frame ECC error mask */ 159#define IMASK_RX_JAB_FRM 0x00000040 /* Rx jabber frame mask */ 160#define IMASK_RX_OVRSZ_FRM 0x00000020 /* Rx oversized frame mask */ 161#define IMASK_RX_RUNT_FRM 0x00000010 /* Rx runt frame mask */ 162#define IMASK_RX_FRAG_FRM 0x00000008 /* Rx fragment frame mask */ 163#define IMASK_RX_LEN_ER 0x00000004 /* Rx payload length error mask */ 164#define IMASK_RX_CRC_ER 0x00000002 /* Rx CRC error mask */ 165#define IMASK_RX_ALIGN_ER 0x00000001 /* Rx alignment error mask */ 166 167#define IMASK_MASK_ALL 0x00000000 168 169/* IEVENT - interrupt event register */ 170#define IEVENT_MDIO_SCAN_EVENT 0x00010000 /* MDIO scan event */ 171#define IEVENT_MDIO_CMD_CMPL 0x00008000 /* MDIO cmd completion */ 172#define IEVENT_REM_FAULT 0x00004000 /* remote fault */ 173#define IEVENT_LOC_FAULT 0x00002000 /* local fault */ 174#define IEVENT_TX_ECC_ER 0x00001000 /* Tx frame ECC error */ 175#define IEVENT_TX_FIFO_UNFL 0x00000800 /* Tx FIFO underflow */ 176#define IEVENT_TX_ER 0x00000200 /* Tx frame error */ 177#define IEVENT_RX_FIFO_OVFL 0x00000100 /* Rx FIFO overflow */ 178#define IEVENT_RX_ECC_ER 0x00000080 /* Rx frame ECC error */ 179#define IEVENT_RX_JAB_FRM 0x00000040 /* Rx jabber frame */ 180#define IEVENT_RX_OVRSZ_FRM 0x00000020 /* Rx oversized frame */ 181#define IEVENT_RX_RUNT_FRM 0x00000010 /* Rx runt frame */ 182#define IEVENT_RX_FRAG_FRM 0x00000008 /* Rx fragment frame */ 183#define IEVENT_RX_LEN_ER 0x00000004 /* Rx payload length error */ 184#define IEVENT_RX_CRC_ER 0x00000002 /* Rx CRC error */ 185#define IEVENT_RX_ALIGN_ER 0x00000001 /* Rx alignment error */ 186 187#define IEVENT_CLEAR_ALL 0xffffffff 188 189struct tgec_mdio_controller { 190 u32 res0[0xc]; 191 u32 mdio_stat; /* MDIO configuration and status */ 192 u32 mdio_ctl; /* MDIO control */ 193 u32 mdio_data; /* MDIO data */ 194 u32 mdio_addr; /* MDIO address */ 195}; 196 197#define MDIO_STAT_CLKDIV(x) (((x>>1) & 0xff) << 8) 198#define MDIO_STAT_BSY (1 << 0) 199#define MDIO_STAT_RD_ER (1 << 1) 200#define MDIO_CTL_DEV_ADDR(x) (x & 0x1f) 201#define MDIO_CTL_PORT_ADDR(x) ((x & 0x1f) << 5) 202#define MDIO_CTL_PRE_DIS (1 << 10) 203#define MDIO_CTL_SCAN_EN (1 << 11) 204#define MDIO_CTL_POST_INC (1 << 14) 205#define MDIO_CTL_READ (1 << 15) 206 207#define MDIO_DATA(x) (x & 0xffff) 208#define MDIO_DATA_BSY (1 << 31) 209 210struct fsl_enet_mac; 211 212void init_tgec(struct fsl_enet_mac *mac, void *base, void *phyregs, 213 int max_rx_len); 214 215#endif 216