LXR uboot/board/cogent/mb.c

   1/*
   2 * (C) Copyright 2000
   3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24#include <common.h>
  25#include <board/cogent/dipsw.h>
  26#include <board/cogent/lcd.h>
  27#include <board/cogent/rtc.h>
  28#include <board/cogent/par.h>
  29#include <board/cogent/pci.h>
  30
  31/* ------------------------------------------------------------------------- */
  32
  33#if defined(CONFIG_8260)
  34
  35#include <ioports.h>
  36
  37/*
  38 * I/O Port configuration table
  39 *
  40 * if conf is 1, then that port pin will be configured at boot time
  41 * according to the five values podr/pdir/ppar/psor/pdat for that entry
  42 */
  43
  44const iop_conf_t iop_conf_tab[4][32] = {
  45
  46        /* Port A configuration */
  47        {                       /*            conf ppar psor pdir podr pdat */
  48         /* PA31 */ {0, 0, 0, 0, 0, 0},
  49         /* PA30 */ {0, 0, 0, 0, 0, 0},
  50         /* PA29 */ {0, 0, 0, 0, 0, 0},
  51         /* PA28 */ {0, 0, 0, 0, 0, 0},
  52         /* PA27 */ {0, 0, 0, 0, 0, 0},
  53         /* PA26 */ {0, 0, 0, 0, 0, 0},
  54         /* PA25 */ {0, 0, 0, 0, 0, 0},
  55         /* PA24 */ {0, 0, 0, 0, 0, 0},
  56         /* PA23 */ {0, 0, 0, 0, 0, 0},
  57         /* PA22 */ {0, 0, 0, 0, 0, 0},
  58         /* PA21 */ {0, 0, 0, 0, 0, 0},
  59         /* PA20 */ {0, 0, 0, 0, 0, 0},
  60         /* PA19 */ {0, 0, 0, 0, 0, 0},
  61         /* PA18 */ {0, 0, 0, 0, 0, 0},
  62         /* PA17 */ {0, 0, 0, 0, 0, 0},
  63         /* PA16 */ {0, 0, 0, 0, 0, 0},
  64         /* PA15 */ {0, 0, 0, 0, 0, 0},
  65         /* PA14 */ {0, 0, 0, 0, 0, 0},
  66         /* PA13 */ {0, 0, 0, 0, 0, 0},
  67         /* PA12 */ {0, 0, 0, 0, 0, 0},
  68         /* PA11 */ {0, 0, 0, 0, 0, 0},
  69         /* PA10 */ {0, 0, 0, 0, 0, 0},
  70                                        /* PA9  */ {1, 1, 0, 1, 0, 0},
  71                                        /* SMC2 TXD */
  72                                        /* PA8  */ {1, 1, 0, 0, 0, 0},
  73                                        /* SMC2 RXD */
  74         /* PA7  */ {0, 0, 0, 0, 0, 0},
  75         /* PA6  */ {0, 0, 0, 0, 0, 0},
  76         /* PA5  */ {0, 0, 0, 0, 0, 0},
  77         /* PA4  */ {0, 0, 0, 0, 0, 0},
  78         /* PA3  */ {0, 0, 0, 0, 0, 0},
  79         /* PA2  */ {0, 0, 0, 0, 0, 0},
  80         /* PA1  */ {0, 0, 0, 0, 0, 0},
  81         /* PA0  */ {0, 0, 0, 0, 0, 0}
  82         },
  83
  84
  85        {                       /*            conf ppar psor pdir podr pdat */
  86         /* PB31 */ {0, 0, 0, 0, 0, 0},
  87         /* PB30 */ {0, 0, 0, 0, 0, 0},
  88         /* PB29 */ {0, 0, 0, 0, 0, 0},
  89         /* PB28 */ {0, 0, 0, 0, 0, 0},
  90         /* PB27 */ {0, 0, 0, 0, 0, 0},
  91         /* PB26 */ {0, 0, 0, 0, 0, 0},
  92         /* PB25 */ {0, 0, 0, 0, 0, 0},
  93         /* PB24 */ {0, 0, 0, 0, 0, 0},
  94         /* PB23 */ {0, 0, 0, 0, 0, 0},
  95         /* PB22 */ {0, 0, 0, 0, 0, 0},
  96         /* PB21 */ {0, 0, 0, 0, 0, 0},
  97         /* PB20 */ {0, 0, 0, 0, 0, 0},
  98         /* PB19 */ {0, 0, 0, 0, 0, 0},
  99         /* PB18 */ {0, 0, 0, 0, 0, 0},
 100         /* PB17 */ {0, 0, 0, 0, 0, 0},
 101         /* PB16 */ {0, 0, 0, 0, 0, 0},
 102         /* PB15 */ {0, 0, 0, 0, 0, 0},
 103         /* PB14 */ {0, 0, 0, 0, 0, 0},
 104         /* PB13 */ {0, 0, 0, 0, 0, 0},
 105         /* PB12 */ {0, 0, 0, 0, 0, 0},
 106         /* PB11 */ {0, 0, 0, 0, 0, 0},
 107         /* PB10 */ {0, 0, 0, 0, 0, 0},
 108         /* PB9  */ {0, 0, 0, 0, 0, 0},
 109         /* PB8  */ {0, 0, 0, 0, 0, 0},
 110         /* PB7  */ {0, 0, 0, 0, 0, 0},
 111         /* PB6  */ {0, 0, 0, 0, 0, 0},
 112         /* PB5  */ {0, 0, 0, 0, 0, 0},
 113         /* PB4  */ {0, 0, 0, 0, 0, 0},
 114                                        /* PB3  */ {0, 0, 0, 0, 0, 0},
 115                                        /* pin doesn't exist */
 116                                        /* PB2  */ {0, 0, 0, 0, 0, 0},
 117                                        /* pin doesn't exist */
 118                                        /* PB1  */ {0, 0, 0, 0, 0, 0},
 119                                        /* pin doesn't exist */
 120                                        /* PB0  */ {0, 0, 0, 0, 0, 0}
 121                                        /* pin doesn't exist */
 122         },
 123
 124
 125        {                       /*            conf ppar psor pdir podr pdat */
 126         /* PC31 */ {0, 0, 0, 0, 0, 0},
 127         /* PC30 */ {0, 0, 0, 0, 0, 0},
 128         /* PC29 */ {0, 0, 0, 0, 0, 0},
 129         /* PC28 */ {0, 0, 0, 0, 0, 0},
 130         /* PC27 */ {0, 0, 0, 0, 0, 0},
 131         /* PC26 */ {0, 0, 0, 0, 0, 0},
 132         /* PC25 */ {0, 0, 0, 0, 0, 0},
 133         /* PC24 */ {0, 0, 0, 0, 0, 0},
 134         /* PC23 */ {0, 0, 0, 0, 0, 0},
 135         /* PC22 */ {0, 0, 0, 0, 0, 0},
 136         /* PC21 */ {0, 0, 0, 0, 0, 0},
 137         /* PC20 */ {0, 0, 0, 0, 0, 0},
 138         /* PC19 */ {0, 0, 0, 0, 0, 0},
 139         /* PC18 */ {0, 0, 0, 0, 0, 0},
 140         /* PC17 */ {0, 0, 0, 0, 0, 0},
 141         /* PC16 */ {0, 0, 0, 0, 0, 0},
 142         /* PC15 */ {0, 0, 0, 0, 0, 0},
 143         /* PC14 */ {0, 0, 0, 0, 0, 0},
 144         /* PC13 */ {0, 0, 0, 0, 0, 0},
 145         /* PC12 */ {0, 0, 0, 0, 0, 0},
 146         /* PC11 */ {0, 0, 0, 0, 0, 0},
 147         /* PC10 */ {0, 0, 0, 0, 0, 0},
 148         /* PC9  */ {0, 0, 0, 0, 0, 0},
 149         /* PC8  */ {0, 0, 0, 0, 0, 0},
 150         /* PC7  */ {0, 0, 0, 0, 0, 0},
 151         /* PC6  */ {0, 0, 0, 0, 0, 0},
 152         /* PC5  */ {0, 0, 0, 0, 0, 0},
 153         /* PC4  */ {0, 0, 0, 0, 0, 0},
 154         /* PC3  */ {0, 0, 0, 0, 0, 0},
 155         /* PC2  */ {0, 0, 0, 0, 0, 0},
 156         /* PC1  */ {0, 0, 0, 0, 0, 0},
 157         /* PC0  */ {0, 0, 0, 0, 0, 0}
 158         },
 159
 160
 161        {                       /*            conf ppar psor pdir podr pdat */
 162         /* PD31 */ {0, 0, 0, 0, 0, 0},
 163         /* PD30 */ {0, 0, 0, 0, 0, 0},
 164         /* PD29 */ {0, 0, 0, 0, 0, 0},
 165         /* PD28 */ {0, 0, 0, 0, 0, 0},
 166         /* PD27 */ {0, 0, 0, 0, 0, 0},
 167         /* PD26 */ {0, 0, 0, 0, 0, 0},
 168         /* PD25 */ {0, 0, 0, 0, 0, 0},
 169         /* PD24 */ {0, 0, 0, 0, 0, 0},
 170         /* PD23 */ {0, 0, 0, 0, 0, 0},
 171         /* PD22 */ {0, 0, 0, 0, 0, 0},
 172         /* PD21 */ {0, 0, 0, 0, 0, 0},
 173         /* PD20 */ {0, 0, 0, 0, 0, 0},
 174         /* PD19 */ {0, 0, 0, 0, 0, 0},
 175         /* PD18 */ {0, 0, 0, 0, 0, 0},
 176         /* PD17 */ {0, 0, 0, 0, 0, 0},
 177         /* PD16 */ {0, 0, 0, 0, 0, 0},
 178                                        /* PD15 */ {1, 1, 1, 0, 0, 0},
 179                                        /* I2C SDA */
 180                                        /* PD14 */ {1, 1, 1, 0, 0, 0},
 181                                        /* I2C SCL */
 182         /* PD13 */ {0, 0, 0, 0, 0, 0},
 183         /* PD12 */ {0, 0, 0, 0, 0, 0},
 184         /* PD11 */ {0, 0, 0, 0, 0, 0},
 185         /* PD10 */ {0, 0, 0, 0, 0, 0},
 186                                        /* PD9  */ {1, 1, 0, 1, 0, 0},
 187                                        /* SMC1 TXD */
 188                                        /* PD8  */ {1, 1, 0, 0, 0, 0},
 189                                        /* SMC1 RXD */
 190         /* PD7  */ {0, 0, 0, 0, 0, 0},
 191         /* PD6  */ {0, 0, 0, 0, 0, 0},
 192         /* PD5  */ {0, 0, 0, 0, 0, 0},
 193         /* PD4  */ {0, 0, 0, 0, 0, 0},
 194                                        /* PD3  */ {0, 0, 0, 0, 0, 0},
 195                                        /* pin doesn't exist */
 196                                        /* PD2  */ {0, 0, 0, 0, 0, 0},
 197                                        /* pin doesn't exist */
 198                                        /* PD1  */ {0, 0, 0, 0, 0, 0},
 199                                        /* pin doesn't exist */
 200                                        /* PD0  */ {0, 0, 0, 0, 0, 0}
 201                                        /* pin doesn't exist */
 202         }
 203};
 204
 205#endif /* CONFIG_8260 */
 206
 207/* ------------------------------------------------------------------------- */
 208
 209/*
 210 * Check Board Identity:
 211 */
 212
 213int checkboard (void)
 214{
 215        puts ("Board: Cogent " COGENT_MOTHERBOARD " motherboard with a "
 216              COGENT_CPU_MODULE " CPU Module\n");
 217        return (0);
 218}
 219
 220/* ------------------------------------------------------------------------- */
 221
 222/*
 223 * Miscelaneous platform dependent initialisations while still
 224 * running in flash
 225 */
 226
 227int misc_init_f (void)
 228{
 229        printf ("DIPSW: ");
 230        dipsw_init ();
 231        return (0);
 232}
 233
 234/* ------------------------------------------------------------------------- */
 235
 236phys_size_t initdram (int board_type)
 237{
 238#ifdef CONFIG_CMA111
 239        return (32L * 1024L * 1024L);
 240#else
 241        unsigned char dipsw_val;
 242        int dual, size0, size1;
 243        long int memsize;
 244
 245        dipsw_val = dipsw_cooked ();
 246
 247        dual = dipsw_val & 0x01;
 248        size0 = (dipsw_val & 0x08) >> 3;
 249        size1 = (dipsw_val & 0x04) >> 2;
 250
 251        if (size0)
 252                if (size1)
 253                        memsize = 16L * 1024L * 1024L;
 254                else
 255                        memsize = 1L * 1024L * 1024L;
 256        else if (size1)
 257                memsize = 4L * 1024L * 1024L;
 258        else {
 259                printf ("[Illegal dip switch settings - assuming 16Mbyte SIMMs] ");
 260                memsize = 16L * 1024L * 1024L;  /* shouldn't happen - guess 16M */
 261        }
 262
 263        if (dual)
 264                memsize *= 2L;
 265
 266        return (memsize);
 267#endif
 268}
 269
 270/* ------------------------------------------------------------------------- */
 271
 272/*
 273 * Miscelaneous platform dependent initialisations after monitor
 274 * has been relocated into ram
 275 */
 276
 277int misc_init_r (void)
 278{
 279        printf ("LCD:   ");
 280        lcd_init ();
 281
 282#if 0
 283        printf ("RTC:   ");
 284        rtc_init ();
 285
 286        printf ("PAR:   ");
 287        par_init ();
 288
 289        printf ("KBM:   ");
 290        kbm_init ();
 291
 292        printf ("PCI:   ");
 293        pci_init ();
 294#endif
 295        return (0);
 296}
 297