LXR uboot/board/davedenx/qong/qong.c

   1/*
   2 *
   3 * (c) 2009 Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24#include <common.h>
  25#include <netdev.h>
  26#include <asm/arch/clock.h>
  27#include <asm/arch/imx-regs.h>
  28#include <asm/arch/sys_proto.h>
  29#include <asm/io.h>
  30#include <nand.h>
  31#include <pmic.h>
  32#include <fsl_pmic.h>
  33#include <asm/gpio.h>
  34#include "qong_fpga.h"
  35#include <watchdog.h>
  36
  37DECLARE_GLOBAL_DATA_PTR;
  38
  39#ifdef CONFIG_HW_WATCHDOG
  40void hw_watchdog_reset(void)
  41{
  42        mxc_hw_watchdog_reset();
  43}
  44#endif
  45
  46int dram_init(void)
  47{
  48        /* dram_init must store complete ramsize in gd->ram_size */
  49        gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  50                                PHYS_SDRAM_1_SIZE);
  51        return 0;
  52}
  53
  54static void qong_fpga_reset(void)
  55{
  56        gpio_set_value(QONG_FPGA_RST_PIN, 0);
  57        udelay(30);
  58        gpio_set_value(QONG_FPGA_RST_PIN, 1);
  59
  60        udelay(300);
  61}
  62
  63int board_early_init_f(void)
  64{
  65#ifdef CONFIG_QONG_FPGA
  66        /* CS1: FPGA/Network Controller/GPIO, 16-bit, no DTACK */
  67        static const struct mxc_weimcs cs1 = {
  68                /*    sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
  69                CSCR_U(0, 0,  0,  0,  0,  0,   0,  0,  0, 10, 0,  0,  1),
  70                /*   oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
  71                CSCR_L(2,  0,   0,   4,  0,  0,  5,  0,  0,  0,   0,   1),
  72                /*  ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
  73                CSCR_A(0,   4,  0,  2,  0,  0,  3,  0,  0,  0,  0,  0,   0,  0)
  74        };
  75
  76        mxc_setup_weimcs(1, &cs1);
  77
  78        /* setup pins for FPGA */
  79        mx31_gpio_mux(IOMUX_MODE(0x76, MUX_CTL_GPIO));
  80        mx31_gpio_mux(IOMUX_MODE(0x7e, MUX_CTL_GPIO));
  81        mx31_gpio_mux(IOMUX_MODE(0x91, MUX_CTL_OUT_FUNC | MUX_CTL_IN_GPIO));
  82        mx31_gpio_mux(IOMUX_MODE(0x92, MUX_CTL_GPIO));
  83        mx31_gpio_mux(IOMUX_MODE(0x93, MUX_CTL_GPIO));
  84
  85        /* FPGA reset  Pin */
  86        /* rstn = 0 */
  87        gpio_direction_output(QONG_FPGA_RST_PIN, 0);
  88
  89        /* set interrupt pin as input */
  90        gpio_direction_input(QONG_FPGA_IRQ_PIN);
  91
  92        /* FPGA JTAG Interface */
  93        mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS6, MUX_CTL_GPIO));
  94        mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK6, MUX_CTL_GPIO));
  95        mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CAPTURE, MUX_CTL_GPIO));
  96        mx31_gpio_mux(IOMUX_MODE(MUX_CTL_COMPARE, MUX_CTL_GPIO));
  97        gpio_direction_output(QONG_FPGA_TCK_PIN, 0);
  98        gpio_direction_output(QONG_FPGA_TMS_PIN, 0);
  99        gpio_direction_output(QONG_FPGA_TDI_PIN, 0);
 100        gpio_direction_input(QONG_FPGA_TDO_PIN);
 101#endif
 102
 103        /* setup pins for UART1 */
 104        mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
 105        mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
 106        mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
 107        mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
 108
 109        /* setup pins for SPI (pmic) */
 110        mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
 111        mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
 112        mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
 113        mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
 114        mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
 115
 116        /* Setup pins for USB2 Host */
 117        mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_CLK, MUX_CTL_FUNC));
 118        mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DIR, MUX_CTL_FUNC));
 119        mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_NXT, MUX_CTL_FUNC));
 120        mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_STP, MUX_CTL_FUNC));
 121        mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA0, MUX_CTL_FUNC));
 122        mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA1, MUX_CTL_FUNC));
 123
 124#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
 125                        PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
 126
 127        mx31_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG);
 128        mx31_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG);
 129        mx31_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG);
 130        mx31_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG);
 131        mx31_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */
 132        mx31_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */
 133        mx31_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG);       /* USBH2_DATA2 */
 134        mx31_set_pad(MX31_PIN_STXD6, H2_PAD_CFG);       /* USBH2_DATA3 */
 135        mx31_set_pad(MX31_PIN_SFS3, H2_PAD_CFG);        /* USBH2_DATA4 */
 136        mx31_set_pad(MX31_PIN_SCK3, H2_PAD_CFG);        /* USBH2_DATA5 */
 137        mx31_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG);       /* USBH2_DATA6 */
 138        mx31_set_pad(MX31_PIN_STXD3, H2_PAD_CFG);       /* USBH2_DATA7 */
 139
 140        mx31_set_gpr(MUX_PGP_UH2, 1);
 141
 142        return 0;
 143
 144}
 145
 146int board_init(void)
 147{
 148        /* Chip selects */
 149        /* CS0: Nor Flash #0 - it must be init'ed when executing from DDR */
 150        /* Assumptions: HCLK = 133 MHz, tACC = 130ns */
 151        static const struct mxc_weimcs cs0 = {
 152                /*     sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
 153                CSCR_U(0, 0,  0,  0,  0,  0,   0,  0,  3, 21, 0,  0,  6),
 154                /*   oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
 155                CSCR_L(0,  1,   3,   3,  1,  1,  5,  1,  0,  0,   0,  1),
 156                /*  ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
 157                CSCR_A(0,   1,  2,  2,  0,  0,  2,  0,  0,  0,  0,  0,   0,  0)
 158        };
 159
 160        mxc_setup_weimcs(0, &cs0);
 161
 162        /* board id for linux */
 163        gd->bd->bi_arch_number = MACH_TYPE_QONG;
 164        gd->bd->bi_boot_params = (0x80000100);  /* adress of boot parameters */
 165
 166        qong_fpga_init();
 167
 168        return 0;
 169}
 170
 171int board_late_init(void)
 172{
 173        u32 val;
 174        struct pmic *p;
 175
 176        pmic_init();
 177        p = get_pmic();
 178
 179        /* Enable RTC battery */
 180        pmic_reg_read(p, REG_POWER_CTL0, &val);
 181        pmic_reg_write(p, REG_POWER_CTL0, val | COINCHEN);
 182        pmic_reg_write(p, REG_INT_STATUS1, RTCRSTI);
 183
 184#ifdef CONFIG_HW_WATCHDOG
 185        mxc_hw_watchdog_enable();
 186#endif
 187
 188        return 0;
 189}
 190
 191int checkboard(void)
 192{
 193        printf("Board: DAVE/DENX Qong\n");
 194        return 0;
 195}
 196
 197int misc_init_r(void)
 198{
 199#ifdef CONFIG_QONG_FPGA
 200        u32 tmp;
 201
 202        tmp = *(volatile u32*)QONG_FPGA_CTRL_VERSION;
 203        printf("FPGA:  ");
 204        printf("version register = %u.%u.%u\n",
 205                (tmp & 0xF000) >> 12, (tmp & 0x0F00) >> 8, tmp & 0x00FF);
 206#endif
 207        return 0;
 208}
 209
 210int board_eth_init(bd_t *bis)
 211{
 212#if defined(CONFIG_QONG_FPGA) && defined(CONFIG_DNET)
 213        return dnet_eth_initialize(0, (void *)CONFIG_DNET_BASE, -1);
 214#else
 215        return 0;
 216#endif
 217}
 218
 219#if defined(CONFIG_QONG_FPGA) && defined(CONFIG_NAND_PLAT)
 220static void board_nand_setup(void)
 221{
 222        /* CS3: NAND 8-bit */
 223        static const struct mxc_weimcs cs3 = {
 224                /*    sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
 225                CSCR_U(0, 0,  0,  0,  0,  0,   0,  0,  1, 15, 0,  0,  0),
 226                /*   oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
 227                CSCR_L(2,  0,   0,   1,  3,  1,  3,  3,  0,  0,   0,   1),
 228                /*  ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
 229                CSCR_A(0,   0,  0,  2,  0,  0,  2,  0,  0,  0,  0,  0,  0,   0)
 230        };
 231
 232        mxc_setup_weimcs(3, &cs3);
 233
 234        mx31_set_gpr(MUX_SDCTL_CSD1_SEL, 1);
 235
 236        mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_WP, MUX_CTL_IN_GPIO));
 237        mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_CE, MUX_CTL_IN_GPIO));
 238        mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_RB, MUX_CTL_IN_GPIO));
 239
 240        /* Make sure to reset the fpga else you cannot access NAND */
 241        qong_fpga_reset();
 242
 243        /* Enable NAND flash */
 244        gpio_set_value(15, 1);
 245        gpio_set_value(14, 1);
 246        gpio_direction_output(15, 0);
 247        gpio_direction_input(16);
 248        gpio_direction_input(14);
 249
 250}
 251
 252int qong_nand_rdy(void *chip)
 253{
 254        udelay(1);
 255        return gpio_get_value(16);
 256}
 257
 258void qong_nand_select_chip(struct mtd_info *mtd, int chip)
 259{
 260        if (chip >= 0)
 261                gpio_set_value(15, 0);
 262        else
 263                gpio_set_value(15, 1);
 264
 265}
 266
 267void qong_nand_plat_init(void *chip)
 268{
 269        struct nand_chip *nand = (struct nand_chip *)chip;
 270        nand->chip_delay = 20;
 271        nand->select_chip = qong_nand_select_chip;
 272        nand->options &= ~NAND_BUSWIDTH_16;
 273        board_nand_setup();
 274}
 275
 276#endif
 277