1/* 2 * Copyright (c) 2000,2001 Epson Research and Development, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 * 22 * Generic Header information generated by 13704CFG.EXE (Build 10) 23 * Panel: 320x240x8bpp 78Hz Mono 8-Bit STN, Disabled (PCLK=6.666MHz) 24 */ 25 26static S1D_REGS regs_13705_320_240_8bpp[] = 27{ 28 { 0x00, 0x00 }, /* Revision Code Register */ 29 { 0x01, 0x23 }, /* Mode Register 0 Register */ 30 { 0x02, 0xE0 }, /* Mode Register 1 Register */ 31 { 0x03, 0x03 }, /* Mode Register 2 Register - bit7 is LUT bypass */ 32 { 0x04, 0x27 }, /* Horizontal Panel Size Register */ 33 { 0x05, 0xEF }, /* Vertical Panel Size Register (LSB) */ 34 { 0x06, 0x00 }, /* Vertical Panel Size Register (MSB) */ 35 { 0x07, 0x00 }, /* FPLINE Start Position Register */ 36 { 0x08, 0x00 }, /* Horizontal Non-Display Period Register */ 37 { 0x09, 0x01 }, /* FPFRAME Start Position Register */ 38 { 0x0A, 0x02 }, /* Vertical Non-Display Period Register */ 39 { 0x0B, 0x00 }, /* MOD Rate Register */ 40 { 0x0C, 0x00 }, /* Screen 1 Start Address Register (LSB) */ 41 { 0x0D, 0x00 }, /* Screen 1 Start Address Register (MSB) */ 42 { 0x0E, 0x00 }, /* Not Used */ 43 { 0x0F, 0x00 }, /* Screen 2 Start Address Register (LSB) */ 44 { 0x10, 0x00 }, /* Screen 2 Start Address Register (MSB) */ 45 { 0x11, 0x00 }, /* Not Used */ 46 { 0x12, 0x00 }, /* Memory Address Offset Register */ 47 { 0x13, 0xFF }, /* Screen 1 Vertical Size Register (LSB) */ 48 { 0x14, 0x03 }, /* Screen 1 Vertical Size Register (MSB) */ 49 { 0x15, 0x00 }, /* Look-Up Table Address Register */ 50 { 0x16, 0x00 }, /* Look-Up Table Bank Select Register */ 51 { 0x17, 0x00 }, /* Look-Up Table Data Register */ 52 { 0x18, 0x01 }, /* GPIO Configuration Control Register */ 53 { 0x19, 0x01 }, /* GPIO Status/Control Register */ 54 { 0x1A, 0x00 }, /* Scratch Pad Register */ 55 { 0x1B, 0x00 }, /* SwivelView Mode Register */ 56 { 0x1C, 0xFF }, /* Line Byte Count Register */ 57 { 0x1D, 0x00 }, /* Not Used */ 58 { 0x1E, 0x00 }, /* Not Used */ 59 { 0x1F, 0x00 }, /* Not Used */ 60}; 61