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24#include <common.h>
25#include <command.h>
26#include <asm/processor.h>
27#include <asm/io.h>
28#include <asm/ppc4xx-gpio.h>
29#include <dtt.h>
30
31#include "405ep.h"
32#include <gdsys_fpga.h>
33
34#include "../common/osd.h"
35
36#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
37#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
38#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
39#define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300)
40
41#define LATCH2_MC2_PRESENT_N 0x0080
42
43enum {
44 UNITTYPE_VIDEO_USER = 0,
45 UNITTYPE_MAIN_USER = 1,
46 UNITTYPE_VIDEO_SERVER = 2,
47 UNITTYPE_MAIN_SERVER = 3,
48};
49
50enum {
51 HWVER_101 = 0,
52 HWVER_110 = 1,
53 HWVER_120 = 2,
54 HWVER_130 = 3,
55};
56
57enum {
58 AUDIO_NONE = 0,
59 AUDIO_TX = 1,
60 AUDIO_RX = 2,
61 AUDIO_RXTX = 3,
62};
63
64enum {
65 SYSCLK_156250 = 2,
66};
67
68enum {
69 RAM_NONE = 0,
70 RAM_DDR2_32 = 1,
71 RAM_DDR2_64 = 2,
72};
73
74int misc_init_r(void)
75{
76
77 dtt_init();
78
79 return 0;
80}
81
82static unsigned int get_hwver(void)
83{
84 u16 latch3 = in_le16((void *)LATCH3_BASE);
85
86 return latch3 & 0x0003;
87}
88
89static unsigned int get_mc2_present(void)
90{
91 u16 latch2 = in_le16((void *)LATCH2_BASE);
92
93 return !(latch2 & LATCH2_MC2_PRESENT_N);
94}
95
96static void print_fpga_info(unsigned dev)
97{
98 struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(dev);
99 u16 versions = in_le16(&fpga->versions);
100 u16 fpga_version = in_le16(&fpga->fpga_version);
101 u16 fpga_features = in_le16(&fpga->fpga_features);
102 unsigned unit_type;
103 unsigned hardware_version;
104 unsigned feature_rs232;
105 unsigned feature_audio;
106 unsigned feature_sysclock;
107 unsigned feature_ramconfig;
108 unsigned feature_carrier_speed;
109 unsigned feature_carriers;
110 unsigned feature_video_channels;
111 int fpga_state = get_fpga_state(dev);
112
113 printf("FPGA%d: ", dev);
114
115 hardware_version = versions & 0x000f;
116
117 if (fpga_state
118 && !((hardware_version == HWVER_101)
119 && (fpga_state == FPGA_STATE_DONE_FAILED))) {
120 puts("not available\n");
121 print_fpga_state(dev);
122 return;
123 }
124
125 unit_type = (versions >> 4) & 0x000f;
126 hardware_version = versions & 0x000f;
127 feature_rs232 = fpga_features & (1<<11);
128 feature_audio = (fpga_features >> 9) & 0x0003;
129 feature_sysclock = (fpga_features >> 7) & 0x0003;
130 feature_ramconfig = (fpga_features >> 5) & 0x0003;
131 feature_carrier_speed = fpga_features & (1<<4);
132 feature_carriers = (fpga_features >> 2) & 0x0003;
133 feature_video_channels = fpga_features & 0x0003;
134
135 switch (unit_type) {
136 case UNITTYPE_VIDEO_USER:
137 printf("Videochannel Userside");
138 break;
139
140 case UNITTYPE_MAIN_USER:
141 printf("Mainchannel Userside");
142 break;
143
144 case UNITTYPE_VIDEO_SERVER:
145 printf("Videochannel Serverside");
146 break;
147
148 case UNITTYPE_MAIN_SERVER:
149 printf("Mainchannel Serverside");
150 break;
151
152 default:
153 printf("UnitType %d(not supported)", unit_type);
154 break;
155 }
156
157 switch (hardware_version) {
158 case HWVER_101:
159 printf(" HW-Ver 1.01\n");
160 break;
161
162 case HWVER_110:
163 printf(" HW-Ver 1.10-1.12\n");
164 break;
165
166 case HWVER_120:
167 printf(" HW-Ver 1.20\n");
168 break;
169
170 case HWVER_130:
171 printf(" HW-Ver 1.30\n");
172 break;
173
174 default:
175 printf(" HW-Ver %d(not supported)\n",
176 hardware_version);
177 break;
178 }
179
180 printf(" FPGA V %d.%02d, features:",
181 fpga_version / 100, fpga_version % 100);
182
183 printf(" %sRS232", feature_rs232 ? "" : "no ");
184
185 switch (feature_audio) {
186 case AUDIO_NONE:
187 printf(", no audio");
188 break;
189
190 case AUDIO_TX:
191 printf(", audio tx");
192 break;
193
194 case AUDIO_RX:
195 printf(", audio rx");
196 break;
197
198 case AUDIO_RXTX:
199 printf(", audio rx+tx");
200 break;
201
202 default:
203 printf(", audio %d(not supported)", feature_audio);
204 break;
205 }
206
207 switch (feature_sysclock) {
208 case SYSCLK_156250:
209 printf(", clock 156.25 MHz");
210 break;
211
212 default:
213 printf(", clock %d(not supported)", feature_sysclock);
214 break;
215 }
216
217 puts(",\n ");
218
219 switch (feature_ramconfig) {
220 case RAM_NONE:
221 printf("no RAM");
222 break;
223
224 case RAM_DDR2_32:
225 printf("RAM 32 bit DDR2");
226 break;
227
228 case RAM_DDR2_64:
229 printf("RAM 64 bit DDR2");
230 break;
231
232 default:
233 printf("RAM %d(not supported)", feature_ramconfig);
234 break;
235 }
236
237 printf(", %d carrier(s) %s", feature_carriers,
238 feature_carrier_speed ? "10 Gbit/s" : "of unknown speed");
239
240 printf(", %d video channel(s)\n", feature_video_channels);
241}
242
243
244
245
246int checkboard(void)
247{
248 char *s = getenv("serial#");
249
250 puts("Board: ");
251
252 puts("DLVision 10G");
253
254 if (s != NULL) {
255 puts(", serial# ");
256 puts(s);
257 }
258
259 puts("\n");
260
261 return 0;
262}
263
264int last_stage_init(void)
265{
266 struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
267 u16 versions = in_le16(&fpga->versions);
268
269 print_fpga_info(0);
270 if (get_mc2_present())
271 print_fpga_info(1);
272
273 if (((versions >> 4) & 0x000f) != UNITTYPE_MAIN_USER)
274 return 0;
275
276 if (!get_fpga_state(0) || (get_hwver() == HWVER_101))
277 osd_probe(0);
278
279 if (get_mc2_present() &&
280 (!get_fpga_state(1) || (get_hwver() == HWVER_101)))
281 osd_probe(1);
282
283 return 0;
284}
285
286void gd405ep_init(void)
287{
288}
289
290void gd405ep_set_fpga_reset(unsigned state)
291{
292 if (state) {
293 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
294 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
295 } else {
296 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
297 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
298 }
299}
300
301void gd405ep_setup_hw(void)
302{
303
304
305
306 gpio_write_bit(21, 0);
307 gpio_write_bit(22, 1);
308}
309
310int gd405ep_get_fpga_done(unsigned fpga)
311{
312 return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
313}
314
