LXR uboot/board/intercontrol/digsy_mtc/digsy

   1/*
   2 * (C) Copyright 2003
   3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4 *
   5 * (C) Copyright 2004
   6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
   7 *
   8 * (C) Copyright 2005-2009
   9 * Modified for InterControl digsyMTC MPC5200 board by
  10 * Frank Bodammer, GCD Hard- & Software GmbH,
  11 *                 frank.bodammer@gcd-solutions.de
  12 *
  13 * (C) Copyright 2009
  14 * Grzegorz Bernacki, Semihalf, gjb@semihalf.com
  15 *
  16 * See file CREDITS for list of people who contributed to this
  17 * project.
  18 *
  19 * This program is free software; you can redistribute it and/or
  20 * modify it under the terms of the GNU General Public License as
  21 * published by the Free Software Foundation; either version 2 of
  22 * the License, or (at your option) any later version.
  23 *
  24 * This program is distributed in the hope that it will be useful,
  25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  27 * GNU General Public License for more details.
  28 *
  29 * You should have received a copy of the GNU General Public License
  30 * along with this program; if not, write to the Free Software
  31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  32 * MA 02111-1307 USA
  33 */
  34
  35#include <common.h>
  36#include <mpc5xxx.h>
  37#include <net.h>
  38#include <pci.h>
  39#include <asm/processor.h>
  40#include <asm/io.h>
  41#include "eeprom.h"
  42#if defined(CONFIG_DIGSY_REV5)
  43#include "is45s16800a2.h"
  44#include <mtd/cfi_flash.h>
  45#include <flash.h>
  46#else
  47#include "is42s16800a-7t.h"
  48#endif
  49#include <libfdt.h>
  50#include <fdt_support.h>
  51#include <i2c.h>
  52#include <mb862xx.h>
  53
  54DECLARE_GLOBAL_DATA_PTR;
  55
  56extern int usb_cpu_init(void);
  57
  58#if defined(CONFIG_DIGSY_REV5)
  59/*
  60 * The M29W128GH needs a specail reset command function,
  61 * details see the doc/README.cfi file
  62 */
  63void flash_cmd_reset(flash_info_t *info)
  64{
  65        flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
  66}
  67#endif
  68
  69#ifndef CONFIG_SYS_RAMBOOT
  70static void sdram_start(int hi_addr)
  71{
  72        long hi_addr_bit = hi_addr ? 0x01000000 : 0;
  73        long control = SDRAM_CONTROL | hi_addr_bit;
  74
  75        /* unlock mode register */
  76        out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);
  77
  78        /* precharge all banks */
  79        out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
  80
  81        /* auto refresh */
  82        out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);
  83
  84        /* set mode register */
  85        out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
  86
  87        /* normal operation */
  88        out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
  89}
  90#endif
  91
  92/*
  93 * ATTENTION: Although partially referenced initdram does NOT make real use
  94 *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if
  95 *            CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
  96 */
  97
  98phys_size_t initdram(int board_type)
  99{
 100        ulong dramsize = 0;
 101        ulong dramsize2 = 0;
 102        uint svr, pvr;
 103#ifndef CONFIG_SYS_RAMBOOT
 104        ulong test1, test2;
 105
 106        /* setup SDRAM chip selects */
 107        out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001C); /* 512MB at 0x0 */
 108        out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */
 109
 110        /* setup config registers */
 111        out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
 112        out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
 113
 114        /* find RAM size using SDRAM CS0 only */
 115        sdram_start(0);
 116        test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
 117        sdram_start(1);
 118        test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
 119        if (test1 > test2) {
 120                sdram_start(0);
 121                dramsize = test1;
 122        } else {
 123                dramsize = test2;
 124        }
 125
 126        /* memory smaller than 1MB is impossible */
 127        if (dramsize < (1 << 20))
 128                dramsize = 0;
 129
 130        /* set SDRAM CS0 size according to the amount of RAM found */
 131        if (dramsize > 0) {
 132                out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
 133                        (0x13 + __builtin_ffs(dramsize >> 20) - 1));
 134        } else {
 135                out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
 136        }
 137
 138        /* let SDRAM CS1 start right after CS0 */
 139        out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize + 0x0000001C);
 140
 141        /* find RAM size using SDRAM CS1 only */
 142        test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize),
 143                        0x08000000);
 144                dramsize2 = test1;
 145
 146        /* memory smaller than 1MB is impossible */
 147        if (dramsize2 < (1 << 20))
 148                dramsize2 = 0;
 149
 150        /* set SDRAM CS1 size according to the amount of RAM found */
 151        if (dramsize2 > 0) {
 152                out_be32((void *)MPC5XXX_SDRAM_CS1CFG, (dramsize |
 153                        (0x13 + __builtin_ffs(dramsize2 >> 20) - 1)));
 154        } else {
 155                out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize); /* disabled */
 156        }
 157
 158#else /* CONFIG_SYS_RAMBOOT */
 159
 160        /* retrieve size of memory connected to SDRAM CS0 */
 161        dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
 162        if (dramsize >= 0x13)
 163                dramsize = (1 << (dramsize - 0x13)) << 20;
 164        else
 165                dramsize = 0;
 166
 167        /* retrieve size of memory connected to SDRAM CS1 */
 168        dramsize2 = in_be32((void *)MPC5XXX_SDRAM_CS1CFG) & 0xFF;
 169        if (dramsize2 >= 0x13)
 170                dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
 171        else
 172                dramsize2 = 0;
 173
 174#endif /* CONFIG_SYS_RAMBOOT */
 175
 176        /*
 177         * On MPC5200B we need to set the special configuration delay in the
 178         * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
 179         * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
 180         *
 181         * "The SDelay should be written to a value of 0x00000004. It is
 182         * required to account for changes caused by normal wafer processing
 183         * parameters."
 184         */
 185        svr = get_svr();
 186        pvr = get_pvr();
 187        if ((SVR_MJREV(svr) >= 2) &&
 188            (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
 189                out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
 190
 191        return dramsize + dramsize2;
 192}
 193
 194int checkboard(void)
 195{
 196        char buf[64];
 197        int i = getenv_f("serial#", buf, sizeof(buf));
 198
 199        puts ("Board: InterControl digsyMTC");
 200#if defined(CONFIG_DIGSY_REV5)
 201        puts (" rev5");
 202#endif
 203        if (i > 0) {
 204                puts(", ");
 205                puts(buf);
 206        }
 207        putc('\n');
 208
 209        return 0;
 210}
 211
 212#if defined(CONFIG_VIDEO)
 213
 214#define GPIO_USB1_0             0x00010000      /* Power-On pin */
 215#define GPIO_USB1_9             0x08            /* PX_~EN pin */
 216
 217#define GPIO_EE_DO              0x10            /* PSC6_0 (DO) pin */
 218#define GPIO_EE_CTS             0x20            /* PSC6_1 (CTS) pin */
 219#define GPIO_EE_DI              0x10000000      /* PSC6_2 (DI) pin */
 220#define GPIO_EE_CLK             0x20000000      /* PSC6_3 (CLK) pin */
 221
 222#define GPT_GPIO_ON             0x00000034      /* GPT as simple GPIO, high */
 223
 224static void exbo_hw_init(void)
 225{
 226        struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT;
 227        struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
 228        struct mpc5xxx_wu_gpio *wu_gpio =
 229                                (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
 230
 231        /* configure IrDA pins (PSC6 port) as gpios */
 232        gpio->port_config &= 0xFF8FFFFF;
 233
 234        /* Init for USB1_0, EE_CLK and EE_DI - Low */
 235        setbits_be32(&gpio->simple_ddr,
 236                        GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
 237        clrbits_be32(&gpio->simple_ode,
 238                        GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
 239        clrbits_be32(&gpio->simple_dvo,
 240                        GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
 241        setbits_be32(&gpio->simple_gpioe,
 242                        GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
 243
 244        /* Init for EE_DO, EE_CTS - Input */
 245        clrbits_8(&wu_gpio->ddr, GPIO_EE_DO | GPIO_EE_CTS);
 246        setbits_8(&wu_gpio->enable, GPIO_EE_DO | GPIO_EE_CTS);
 247
 248        /* Init for PX_~EN (USB1_9) - High */
 249        clrbits_8(&gpio->sint_ode, GPIO_USB1_9);
 250        setbits_8(&gpio->sint_ddr, GPIO_USB1_9);
 251        clrbits_8(&gpio->sint_inten, GPIO_USB1_9);
 252        setbits_8(&gpio->sint_dvo, GPIO_USB1_9);
 253        setbits_8(&gpio->sint_gpioe, GPIO_USB1_9);
 254
 255        /* Init for ~OE Switch (GPIO3) - Timer_0 GPIO High */
 256        out_be32(&gpt[0].emsr, GPT_GPIO_ON);
 257        /* Init for S Switch (GPIO4) - Timer_1 GPIO High */
 258        out_be32(&gpt[1].emsr, GPT_GPIO_ON);
 259
 260        /* Power-On camera supply */
 261        setbits_be32(&gpio->simple_dvo, GPIO_USB1_0);
 262}
 263#else
 264static inline void exbo_hw_init(void) {}
 265#endif /* CONFIG_VIDEO */
 266
 267int board_early_init_r(void)
 268{
 269#ifdef CONFIG_MPC52XX_SPI
 270        struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt*)MPC5XXX_GPT;
 271#endif
 272        /*
 273         * Now, when we are in RAM, enable flash write access for detection
 274         * process.  Note that CS_BOOT cannot be cleared when executing in
 275         * flash.
 276         */
 277        /* disable CS_BOOT */
 278        clrbits_be32((void *)MPC5XXX_ADDECR, (1 << 25));
 279        /* enable CS1 */
 280        setbits_be32((void *)MPC5XXX_ADDECR, (1 << 17));
 281        /* enable CS0 */
 282        setbits_be32((void *)MPC5XXX_ADDECR, (1 << 16));
 283
 284#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
 285        /* Low level USB init, required for proper kernel operation */
 286        usb_cpu_init();
 287#endif
 288#ifdef CONFIG_MPC52XX_SPI
 289        /* GPT 6 Output Enable */
 290        out_be32(&gpt[6].emsr, 0x00000034);
 291        /* GPT 7 Output Enable */
 292        out_be32(&gpt[7].emsr, 0x00000034);
 293#endif
 294
 295        return (0);
 296}
 297
 298void board_get_enetaddr (uchar * enet)
 299{
 300        ushort read = 0;
 301        ushort addr_of_eth_addr = 0;
 302        ushort len_sys = 0;
 303        ushort len_sys_cfg = 0;
 304
 305        /* check identification word */
 306        eeprom_read(EEPROM_ADDR, EEPROM_ADDR_IDENT, (uchar *)&read, 2);
 307        if (read != EEPROM_IDENT)
 308                return;
 309
 310        /* calculate offset of config area */
 311        eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYS, (uchar *)&len_sys, 2);
 312        eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYSCFG,
 313                (uchar *)&len_sys_cfg, 2);
 314        addr_of_eth_addr = (len_sys + len_sys_cfg + EEPROM_ADDR_ETHADDR) << 1;
 315        if (addr_of_eth_addr >= EEPROM_LEN)
 316                return;
 317
 318        eeprom_read(EEPROM_ADDR, addr_of_eth_addr, enet, 6);
 319}
 320
 321int misc_init_r(void)
 322{
 323        pci_dev_t devbusfn;
 324        uchar enetaddr[6];
 325
 326        /* check if graphic extension board is present */
 327        devbusfn = pci_find_device(PCI_VENDOR_ID_FUJITSU,
 328                                   PCI_DEVICE_ID_CORAL_PA, 0);
 329        if (devbusfn != -1)
 330                exbo_hw_init();
 331
 332        if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
 333                board_get_enetaddr(enetaddr);
 334                eth_setenv_enetaddr("ethaddr", enetaddr);
 335        }
 336
 337        return 0;
 338}
 339
 340#ifdef CONFIG_PCI
 341static struct pci_controller hose;
 342
 343extern void pci_mpc5xxx_init(struct pci_controller *);
 344
 345void pci_init_board(void)
 346{
 347        pci_mpc5xxx_init(&hose);
 348}
 349#endif
 350
 351#ifdef CONFIG_CMD_IDE
 352
 353#ifdef CONFIG_IDE_RESET
 354
 355void init_ide_reset(void)
 356{
 357        debug ("init_ide_reset\n");
 358
 359        /* set gpio output value to 1 */
 360        setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
 361        /* open drain output */
 362        setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
 363        /* direction output */
 364        setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
 365        /* enable gpio */
 366        setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
 367
 368}
 369
 370void ide_set_reset(int idereset)
 371{
 372        debug ("ide_reset(%d)\n", idereset);
 373
 374        /* set gpio output value to 0 */
 375        clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
 376        /* open drain output */
 377        setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
 378        /* direction output */
 379        setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
 380        /* enable gpio */
 381        setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
 382
 383        udelay(10000);
 384
 385        /* set gpio output value to 1 */
 386        setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
 387        /* open drain output */
 388        setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
 389        /* direction output */
 390        setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
 391        /* enable gpio */
 392        setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
 393}
 394#endif /* CONFIG_IDE_RESET */
 395#endif /* CONFIG_CMD_IDE */
 396
 397#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 398static void ft_delete_node(void *fdt, const char *compat)
 399{
 400        int off = -1;
 401        int ret;
 402
 403        off = fdt_node_offset_by_compatible(fdt, -1, compat);
 404        if (off < 0) {
 405                printf("Could not find %s node.\n", compat);
 406                return;
 407        }
 408
 409        ret = fdt_del_node(fdt, off);
 410        if (ret < 0)
 411                printf("Could not delete %s node.\n", compat);
 412}
 413#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
 414static void ft_adapt_flash_base(void *blob)
 415{
 416        flash_info_t    *dev = &flash_info[0];
 417        int off;
 418        struct fdt_property *prop;
 419        int len;
 420        u32 *reg, *reg2;
 421
 422        off = fdt_node_offset_by_compatible(blob, -1, "fsl,mpc5200b-lpb");
 423        if (off < 0) {
 424                printf("Could not find fsl,mpc5200b-lpb node.\n");
 425                return;
 426        }
 427
 428        /* found compatible property */
 429        prop = fdt_get_property_w(blob, off, "ranges", &len);
 430        if (prop) {
 431                reg = reg2 = (u32 *)&prop->data[0];
 432
 433                reg[2] = dev->start[0];
 434                reg[3] = dev->size;
 435                fdt_setprop(blob, off, "ranges", reg2, len);
 436        } else
 437                printf("Could not find ranges\n");
 438}
 439
 440extern ulong flash_get_size (phys_addr_t base, int banknum);
 441
 442/* Update the Flash Baseaddr settings */
 443int update_flash_size (int flash_size)
 444{
 445        volatile struct mpc5xxx_mmap_ctl *mm =
 446                (struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
 447        flash_info_t    *dev;
 448        int     i;
 449        int size = 0;
 450        unsigned long base = 0x0;
 451        u32 *cs_reg = (u32 *)&mm->cs0_start;
 452
 453        for (i = 0; i < 2; i++) {
 454                dev = &flash_info[i];
 455
 456                if (dev->size) {
 457                        /* calculate new base addr for this chipselect */
 458                        base -= dev->size;
 459                        out_be32(cs_reg, START_REG(base));
 460                        cs_reg++;
 461                        out_be32(cs_reg, STOP_REG(base, dev->size));
 462                        cs_reg++;
 463                        /* recalculate the sectoraddr in the cfi driver */
 464                        size += flash_get_size(base, i);
 465                }
 466        }
 467        flash_protect_default();
 468        gd->bd->bi_flashstart = base;
 469        return 0;
 470}
 471#endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */
 472
 473void ft_board_setup(void *blob, bd_t *bd)
 474{
 475        int phy_addr = CONFIG_PHY_ADDR;
 476        char eth_path[] = "/soc5200@f0000000/mdio@3000/ethernet-phy@0";
 477
 478        ft_cpu_setup(blob, bd);
 479        /*
 480         * There are 2 RTC nodes in the DTS, so remove
 481         * the unneeded node here.
 482         */
 483#if defined(CONFIG_DIGSY_REV5)
 484        ft_delete_node(blob, "dallas,ds1339");
 485#else
 486        ft_delete_node(blob, "mc,rv3029c2");
 487#endif
 488#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
 489#ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
 490        /* Update reg property in all nor flash nodes too */
 491        fdt_fixup_nor_flash_size(blob);
 492#endif
 493        ft_adapt_flash_base(blob);
 494#endif
 495        /* fix up the phy address */
 496        do_fixup_by_path(blob, eth_path, "reg", &phy_addr, sizeof(int), 0);
 497}
 498#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
 499