LXR uboot/board/linkstation/linkstation.c

   1/*
   2 * linkstation.c
   3 *
   4 * Misc LinkStation specific functions
   5 *
   6 * Copyright (C) 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk>
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24#include <common.h>
  25#include <version.h>
  26#include <mpc824x.h>
  27#include <asm/io.h>
  28#include <ns16550.h>
  29#include <netdev.h>
  30
  31#ifdef CONFIG_PCI
  32#include <pci.h>
  33#endif
  34
  35DECLARE_GLOBAL_DATA_PTR;
  36
  37extern void init_AVR_DUART(void);
  38
  39int checkboard (void)
  40{
  41        char *p;
  42        bd_t *bd = gd->bd;
  43
  44        init_AVR_DUART();
  45
  46        if ((p = getenv ("console_nr")) != NULL) {
  47                unsigned long con_nr = simple_strtoul (p, NULL, 10) & 3;
  48
  49                bd->bi_baudrate &= ~3;
  50                bd->bi_baudrate |= con_nr & 3;
  51        }
  52        return 0;
  53}
  54
  55phys_size_t initdram (int board_type)
  56{
  57        return (get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE));
  58}
  59
  60/*
  61 * Initialize PCI Devices
  62 */
  63#ifdef CONFIG_PCI
  64
  65#ifndef CONFIG_PCI_PNP
  66
  67static struct pci_config_table pci_linkstation_config_table[] = {
  68        /* vendor, device, class */
  69        /* bus, dev, func */
  70        { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
  71          PCI_ANY_ID, 0x0b, 0,          /* AN983B or RTL8110S  */
  72                                                                /* ethernet controller */
  73          pci_cfgfunc_config_device, { PCI_ETH_IOADDR,
  74                                       PCI_ETH_MEMADDR,
  75                                       PCI_COMMAND_IO |
  76                                       PCI_COMMAND_MEMORY |
  77                                       PCI_COMMAND_MASTER }},
  78        { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
  79          PCI_ANY_ID, 0x0c, 0,          /* SII680 or IT8211AF */
  80                                                                /* ide controller     */
  81          pci_cfgfunc_config_device, { PCI_IDE_IOADDR,
  82                                       PCI_IDE_MEMADDR,
  83                                       PCI_COMMAND_IO |
  84                                       PCI_COMMAND_MEMORY |
  85                                       PCI_COMMAND_MASTER }},
  86        { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
  87          PCI_ANY_ID, 0x0e, 0,          /* D720101 USB controller, 1st USB 1.1 */
  88          pci_cfgfunc_config_device, { PCI_USB0_IOADDR,
  89                                       PCI_USB0_MEMADDR,
  90                                       PCI_COMMAND_MEMORY |
  91                                       PCI_COMMAND_MASTER }},
  92        { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
  93          PCI_ANY_ID, 0x0e, 1,          /* D720101 USB controller, 2nd USB 1.1 */
  94          pci_cfgfunc_config_device, { PCI_USB1_IOADDR,
  95                                       PCI_USB1_MEMADDR,
  96                                       PCI_COMMAND_MEMORY |
  97                                       PCI_COMMAND_MASTER }},
  98        { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
  99          PCI_ANY_ID, 0x0e, 2,          /* D720101 USB controller, USB 2.0 */
 100          pci_cfgfunc_config_device, { PCI_USB2_IOADDR,
 101                                       PCI_USB2_MEMADDR,
 102                                       PCI_COMMAND_MEMORY |
 103                                       PCI_COMMAND_MASTER }},
 104        { }
 105};
 106#endif
 107
 108struct pci_controller hose = {
 109#ifndef CONFIG_PCI_PNP
 110        config_table:pci_linkstation_config_table,
 111#endif
 112};
 113
 114void pci_init_board (void)
 115{
 116        pci_mpc824x_init (&hose);
 117
 118        /* Reset USB 1.1 */
 119        /* Haven't seen any change without these on a HG, maybe it is
 120         * needed on other models */
 121        out_le32((volatile unsigned*)(PCI_USB0_MEMADDR + 8), 1);
 122        out_le32((volatile unsigned*)(PCI_USB1_MEMADDR + 8), 1);
 123}
 124#endif /* CONFIG_PCI */
 125
 126#define UART_DCR       0x80004511
 127int board_early_init_f (void)
 128{
 129        /* set DUART mode */
 130        out_8((volatile u8*)UART_DCR, 1);
 131        return 0;
 132}
 133
 134int board_eth_init(bd_t *bis)
 135{
 136        return pci_eth_init(bis);
 137}
 138