LXR uboot/board/ronetix/pm9263/pm9263.c

   1/*
   2 * (C) Copyright 2007-2008
   3 * Stelian Pop <stelian@popies.net>
   4 * Lead Tech Design <www.leadtechdesign.com>
   5 * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
   6 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
   7 *
   8 * See file CREDITS for list of people who contributed to this
   9 * project.
  10 *
  11 * This program is free software; you can redistribute it and/or
  12 * modify it under the terms of the GNU General Public License as
  13 * published by the Free Software Foundation; either version 2 of
  14 * the License, or (at your option) any later version.
  15 *
  16 * This program is distributed in the hope that it will be useful,
  17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19 * GNU General Public License for more details.
  20 *
  21 * You should have received a copy of the GNU General Public License
  22 * along with this program; if not, write to the Free Software
  23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24 * MA 02111-1307 USA
  25 */
  26
  27#include <common.h>
  28#include <asm/sizes.h>
  29#include <asm/io.h>
  30#include <asm/arch/at91sam9_smc.h>
  31#include <asm/arch/at91_common.h>
  32#include <asm/arch/at91_pmc.h>
  33#include <asm/arch/at91_rstc.h>
  34#include <asm/arch/at91_matrix.h>
  35#include <asm/arch/clk.h>
  36#include <asm/arch/gpio.h>
  37#include <lcd.h>
  38#include <atmel_lcdc.h>
  39#include <dataflash.h>
  40#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
  41#include <net.h>
  42#endif
  43#include <netdev.h>
  44
  45DECLARE_GLOBAL_DATA_PTR;
  46
  47/* ------------------------------------------------------------------------- */
  48/*
  49 * Miscelaneous platform dependent initialisations
  50 */
  51
  52#ifdef CONFIG_CMD_NAND
  53static void pm9263_nand_hw_init(void)
  54{
  55        unsigned long csa;
  56        struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC0;
  57        struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  58
  59        /* Enable CS3 */
  60        csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
  61        writel(csa, &matrix->csa[0]);
  62
  63        /* Configure SMC CS3 for NAND/SmartMedia */
  64        writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
  65                AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
  66                &smc->cs[3].setup);
  67
  68        writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  69                AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  70                &smc->cs[3].pulse);
  71
  72        writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  73                &smc->cs[3].cycle);
  74
  75        writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  76                AT91_SMC_MODE_EXNW_DISABLE |
  77#ifdef CONFIG_SYS_NAND_DBW_16
  78                AT91_SMC_MODE_DBW_16 |
  79#else /* CONFIG_SYS_NAND_DBW_8 */
  80                AT91_SMC_MODE_DBW_8 |
  81#endif
  82                AT91_SMC_MODE_TDF_CYCLE(2),
  83                &smc->cs[3].mode);
  84
  85        /* Configure RDY/BSY */
  86        at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  87
  88        /* Enable NandFlash */
  89        at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  90}
  91#endif
  92
  93#ifdef CONFIG_MACB
  94static void pm9263_macb_hw_init(void)
  95{
  96        struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  97
  98        /*
  99         * PB27 enables the 50MHz oscillator for Ethernet PHY
 100         * 1 - enable
 101         * 0 - disable
 102         */
 103        at91_set_pio_output(AT91_PIO_PORTB, 27, 1);
 104        at91_set_pio_value(AT91_PIO_PORTB, 27, 1); /* 1- enable, 0 - disable */
 105
 106        /* Enable clock */
 107        writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
 108
 109        /*
 110         * Disable pull-up on:
 111         *      RXDV (PC25) => PHY normal mode (not Test mode)
 112         *      ERX0 (PE25) => PHY ADDR0
 113         *      ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
 114         *
 115         * PHY has internal pull-down
 116         */
 117
 118        at91_set_pio_pullup(AT91_PIO_PORTC, 25, 0);
 119        at91_set_pio_pullup(AT91_PIO_PORTE, 25, 0);
 120        at91_set_pio_pullup(AT91_PIO_PORTE, 26, 0);
 121
 122        /* Re-enable pull-up */
 123        at91_set_pio_pullup(AT91_PIO_PORTC, 25, 1);
 124        at91_set_pio_pullup(AT91_PIO_PORTE, 25, 1);
 125        at91_set_pio_pullup(AT91_PIO_PORTE, 26, 1);
 126
 127        at91_macb_hw_init();
 128}
 129#endif
 130
 131#ifdef CONFIG_LCD
 132vidinfo_t panel_info = {
 133        vl_col:         240,
 134        vl_row:         320,
 135        vl_clk:         4965000,
 136        vl_sync:        ATMEL_LCDC_INVLINE_INVERTED |
 137                        ATMEL_LCDC_INVFRAME_INVERTED,
 138        vl_bpix:        3,
 139        vl_tft:         1,
 140        vl_hsync_len:   5,
 141        vl_left_margin: 1,
 142        vl_right_margin:33,
 143        vl_vsync_len:   1,
 144        vl_upper_margin:1,
 145        vl_lower_margin:0,
 146        mmio:           ATMEL_BASE_LCDC,
 147};
 148
 149void lcd_enable(void)
 150{
 151        at91_set_pio_value(AT91_PIO_PORTA, 22, 1); /* power up */
 152}
 153
 154void lcd_disable(void)
 155{
 156        at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */
 157}
 158
 159#ifdef CONFIG_LCD_IN_PSRAM
 160
 161#define PSRAM_CRE_PIN   AT91_PIO_PORTB, 29
 162#define PSRAM_CTRL_REG  (PHYS_PSRAM + PHYS_PSRAM_SIZE - 2)
 163
 164/* Initialize the PSRAM memory */
 165static int pm9263_lcd_hw_psram_init(void)
 166{
 167        unsigned long csa;
 168        struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC1;
 169        struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
 170
 171        /* Enable CS3  3.3v, no pull-ups */
 172        csa = readl(&matrix->csa[1]) | AT91_MATRIX_CSA_DBPUC |
 173                AT91_MATRIX_CSA_VDDIOMSEL_3_3V;
 174
 175        writel(csa, &matrix->csa[1]);
 176
 177        /* Configure SMC1 CS0 for PSRAM - 16-bit */
 178        writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
 179                AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
 180                &smc->cs[0].setup);
 181
 182        writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) |
 183                AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(7),
 184                &smc->cs[0].pulse);
 185
 186        writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
 187                &smc->cs[0].cycle);
 188
 189        writel(AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_PMEN | AT91_SMC_MODE_PS_32,
 190                &smc->cs[0].mode);
 191
 192        /* setup PB29 as output */
 193        at91_set_pio_output(PSRAM_CRE_PIN, 1);
 194
 195        at91_set_pio_value(PSRAM_CRE_PIN, 0);   /* set PSRAM_CRE_PIN to '0' */
 196
 197        /* PSRAM: write BCR */
 198        readw(PSRAM_CTRL_REG);
 199        readw(PSRAM_CTRL_REG);
 200        writew(1, PSRAM_CTRL_REG);      /* 0 - RCR,1 - BCR */
 201        writew(0x9d4f, PSRAM_CTRL_REG); /* write the BCR */
 202
 203        /* write RCR of the PSRAM */
 204        readw(PSRAM_CTRL_REG);
 205        readw(PSRAM_CTRL_REG);
 206        writew(0, PSRAM_CTRL_REG);      /* 0 - RCR,1 - BCR */
 207        /* set RCR; 0x10-async mode,0x90-page mode */
 208        writew(0x90, PSRAM_CTRL_REG);
 209
 210        /*
 211         * test to see if the PSRAM is MT45W2M16A or MT45W2M16B
 212         * MT45W2M16B - CRE must be 0
 213         * MT45W2M16A - CRE must be 1
 214         */
 215        writew(0x1234, PHYS_PSRAM);
 216        writew(0x5678, PHYS_PSRAM + 2);
 217
 218        /* test if the chip is MT45W2M16B */
 219        if ((readw(PHYS_PSRAM) != 0x1234) || (readw(PHYS_PSRAM+2) != 0x5678)) {
 220                /* try with CRE=1 (MT45W2M16A) */
 221                at91_set_pio_value(PSRAM_CRE_PIN, 1); /* set PSRAM_CRE_PIN to '1' */
 222
 223                /* write RCR of the PSRAM */
 224                readw(PSRAM_CTRL_REG);
 225                readw(PSRAM_CTRL_REG);
 226                writew(0, PSRAM_CTRL_REG);      /* 0 - RCR,1 - BCR */
 227                /* set RCR;0x10-async mode,0x90-page mode */
 228                writew(0x90, PSRAM_CTRL_REG);
 229
 230
 231                writew(0x1234, PHYS_PSRAM);
 232                writew(0x5678, PHYS_PSRAM+2);
 233                if ((readw(PHYS_PSRAM) != 0x1234)
 234                  || (readw(PHYS_PSRAM + 2) != 0x5678))
 235                        return 1;
 236
 237        }
 238
 239        /* Bus matrix */
 240        writel(AT91_MATRIX_PRA_M5(3), &matrix->pr[5].a);
 241        writel(CONFIG_PSRAM_SCFG, &matrix->scfg[5]);
 242
 243        return 0;
 244}
 245#endif
 246
 247static void pm9263_lcd_hw_init(void)
 248{
 249        struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 250
 251        at91_set_a_periph(AT91_PIO_PORTC, 0, 0);        /* LCDVSYNC */
 252        at91_set_a_periph(AT91_PIO_PORTC, 1, 0);        /* LCDHSYNC */
 253        at91_set_a_periph(AT91_PIO_PORTC, 2, 0);        /* LCDDOTCK */
 254        at91_set_a_periph(AT91_PIO_PORTC, 3, 0);        /* LCDDEN */
 255        at91_set_b_periph(AT91_PIO_PORTB, 9, 0);        /* LCDCC */
 256        at91_set_a_periph(AT91_PIO_PORTC, 6, 0);        /* LCDD2 */
 257        at91_set_a_periph(AT91_PIO_PORTC, 7, 0);        /* LCDD3 */
 258        at91_set_a_periph(AT91_PIO_PORTC, 8, 0);        /* LCDD4 */
 259        at91_set_a_periph(AT91_PIO_PORTC, 9, 0);        /* LCDD5 */
 260        at91_set_a_periph(AT91_PIO_PORTC, 10, 0);       /* LCDD6 */
 261        at91_set_a_periph(AT91_PIO_PORTC, 11, 0);       /* LCDD7 */
 262        at91_set_a_periph(AT91_PIO_PORTC, 14, 0);       /* LCDD10 */
 263        at91_set_a_periph(AT91_PIO_PORTC, 15, 0);       /* LCDD11 */
 264        at91_set_a_periph(AT91_PIO_PORTC, 16, 0);       /* LCDD12 */
 265        at91_set_b_periph(AT91_PIO_PORTC, 12, 0);       /* LCDD13 */
 266        at91_set_a_periph(AT91_PIO_PORTC, 18, 0);       /* LCDD14 */
 267        at91_set_a_periph(AT91_PIO_PORTC, 19, 0);       /* LCDD15 */
 268        at91_set_a_periph(AT91_PIO_PORTC, 22, 0);       /* LCDD18 */
 269        at91_set_a_periph(AT91_PIO_PORTC, 23, 0);       /* LCDD19 */
 270        at91_set_a_periph(AT91_PIO_PORTC, 24, 0);       /* LCDD20 */
 271        at91_set_b_periph(AT91_PIO_PORTC, 17, 0);       /* LCDD21 */
 272        at91_set_a_periph(AT91_PIO_PORTC, 26, 0);       /* LCDD22 */
 273        at91_set_a_periph(AT91_PIO_PORTC, 27, 0);       /* LCDD23 */
 274
 275        writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
 276
 277        /* Power Control */
 278        at91_set_pio_output(AT91_PIO_PORTA, 22, 1);
 279        at91_set_pio_value(AT91_PIO_PORTA, 22, 0);      /* power down */
 280
 281#ifdef CONFIG_LCD_IN_PSRAM
 282        /* initialize te PSRAM */
 283        int stat = pm9263_lcd_hw_psram_init();
 284
 285        gd->fb_base = (stat == 0) ? PHYS_PSRAM : ATMEL_BASE_SRAM0;
 286#else
 287        gd->fb_base = ATMEL_BASE_SRAM0;
 288#endif
 289
 290}
 291
 292#ifdef CONFIG_LCD_INFO
 293#include <nand.h>
 294#include <version.h>
 295
 296extern flash_info_t flash_info[];
 297
 298void lcd_show_board_info(void)
 299{
 300        ulong dram_size, nand_size, flash_size, dataflash_size;
 301        int i;
 302        char temp[32];
 303
 304        lcd_printf ("%s\n", U_BOOT_VERSION);
 305        lcd_printf ("(C) 2009 Ronetix GmbH\n");
 306        lcd_printf ("support@ronetix.at\n");
 307        lcd_printf ("%s CPU at %s MHz",
 308                CONFIG_SYS_AT91_CPU_NAME,
 309                strmhz(temp, get_cpu_clk_rate()));
 310
 311        dram_size = 0;
 312        for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 313                dram_size += gd->bd->bi_dram[i].size;
 314
 315        nand_size = 0;
 316        for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 317                nand_size += nand_info[i].size;
 318
 319        flash_size = 0;
 320        for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
 321                flash_size += flash_info[i].size;
 322
 323        dataflash_size = 0;
 324        for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++)
 325                dataflash_size += (unsigned int) dataflash_info[i].Device.pages_number *
 326                                dataflash_info[i].Device.pages_size;
 327
 328        lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n"
 329                        "4 MB PSRAM, %ld MB DataFlash\n",
 330                dram_size >> 20,
 331                nand_size >> 20,
 332                flash_size >> 20,
 333                dataflash_size >> 20);
 334}
 335#endif /* CONFIG_LCD_INFO */
 336
 337#endif /* CONFIG_LCD */
 338
 339int board_early_init_f(void)
 340{
 341        struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 342
 343        /* Enable clocks for all PIOs */
 344        writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
 345                (1 << ATMEL_ID_PIOCDE),
 346                &pmc->pcer);
 347
 348        at91_seriald_hw_init();
 349
 350        return 0;
 351}
 352
 353int board_init(void)
 354{
 355        /* arch number of AT91SAM9263EK-Board */
 356        gd->bd->bi_arch_number = MACH_TYPE_PM9263;
 357
 358        /* adress of boot parameters */
 359        gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 360
 361#ifdef CONFIG_CMD_NAND
 362        pm9263_nand_hw_init();
 363#endif
 364#ifdef CONFIG_HAS_DATAFLASH
 365        at91_spi0_hw_init(1 << 0);
 366#endif
 367#ifdef CONFIG_MACB
 368        pm9263_macb_hw_init();
 369#endif
 370#ifdef CONFIG_USB_OHCI_NEW
 371        at91_uhp_hw_init();
 372#endif
 373#ifdef CONFIG_LCD
 374        pm9263_lcd_hw_init();
 375#endif
 376        return 0;
 377}
 378
 379int dram_init(void)
 380{
 381        /* dram_init must store complete ramsize in gd->ram_size */
 382        gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
 383                                PHYS_SDRAM_SIZE);
 384        return 0;
 385}
 386
 387void dram_init_banksize(void)
 388{
 389        gd->bd->bi_dram[0].start = PHYS_SDRAM;
 390        gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
 391}
 392
 393#ifdef CONFIG_RESET_PHY_R
 394void reset_phy(void)
 395{
 396}
 397#endif
 398
 399int board_eth_init(bd_t *bis)
 400{
 401        int rc = 0;
 402#ifdef CONFIG_MACB
 403        rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x01);
 404#endif
 405        return rc;
 406}
 407
 408#ifdef CONFIG_DISPLAY_BOARDINFO
 409int checkboard (void)
 410{
 411        char *ss;
 412
 413        printf ("Board : Ronetix PM9263\n");
 414
 415        switch (gd->fb_base) {
 416        case PHYS_PSRAM:
 417                ss = "(PSRAM)";
 418                break;
 419
 420        case ATMEL_BASE_SRAM0:
 421                ss = "(Internal SRAM)";
 422                break;
 423
 424        default:
 425                ss = "";
 426                break;
 427        }
 428        printf("Video memory : 0x%08lX %s\n", gd->fb_base, ss );
 429
 430        printf ("\n");
 431        return 0;
 432}
 433#endif
 434