LXR uboot/board/samsung/smdk6400/lowlevel

   1/*
   2 * Memory Setup stuff - taken from blob memsetup.S
   3 *
   4 * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
   5 *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
   6 *
   7 * Modified for the Samsung SMDK2410 by
   8 * (C) Copyright 2002
   9 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
  10 *
  11 * (C) Copyright 2008
  12 * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
  13 *
  14 * See file CREDITS for list of people who contributed to this
  15 * project.
  16 *
  17 * This program is free software; you can redistribute it and/or
  18 * modify it under the terms of the GNU General Public License as
  19 * published by the Free Software Foundation; either version 2 of
  20 * the License, or (at your option) any later version.
  21 *
  22 * This program is distributed in the hope that it will be useful,
  23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  25 * GNU General Public License for more details.
  26 *
  27 * You should have received a copy of the GNU General Public License
  28 * along with this program; if not, write to the Free Software
  29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  30 * MA 02111-1307 USA
  31 */
  32
  33
  34#include <config.h>
  35#include <version.h>
  36
  37#include <asm/arch/s3c6400.h>
  38
  39#ifdef CONFIG_SERIAL1
  40#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART0_OFFSET)
  41#elif defined(CONFIG_SERIAL2)
  42#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART1_OFFSET)
  43#else
  44#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART2_OFFSET)
  45#endif
  46
  47_TEXT_BASE:
  48        .word   CONFIG_SYS_TEXT_BASE
  49
  50        .globl lowlevel_init
  51lowlevel_init:
  52        mov     r12, lr
  53
  54        /* LED on only #8 */
  55        ldr     r0, =ELFIN_GPIO_BASE
  56        ldr     r1, =0x55540000
  57        str     r1, [r0, #GPNCON_OFFSET]
  58
  59        ldr     r1, =0x55555555
  60        str     r1, [r0, #GPNPUD_OFFSET]
  61
  62        ldr     r1, =0xf000
  63        str     r1, [r0, #GPNDAT_OFFSET]
  64
  65        /* Disable Watchdog */
  66        ldr     r0, =0x7e000000         @0x7e004000
  67        orr     r0, r0, #0x4000
  68        mov     r1, #0
  69        str     r1, [r0]
  70
  71        /* External interrupt pending clear */
  72        ldr     r0, =(ELFIN_GPIO_BASE+EINTPEND_OFFSET)  /*EINTPEND*/
  73        ldr     r1, [r0]
  74        str     r1, [r0]
  75
  76        ldr     r0, =ELFIN_VIC0_BASE_ADDR       @0x71200000
  77        ldr     r1, =ELFIN_VIC1_BASE_ADDR       @0x71300000
  78
  79        /* Disable all interrupts (VIC0 and VIC1) */
  80        mvn     r3, #0x0
  81        str     r3, [r0, #oINTMSK]
  82        str     r3, [r1, #oINTMSK]
  83
  84        /* Set all interrupts as IRQ */
  85        mov     r3, #0x0
  86        str     r3, [r0, #oINTMOD]
  87        str     r3, [r1, #oINTMOD]
  88
  89        /* Pending Interrupt Clear */
  90        mov     r3, #0x0
  91        str     r3, [r0, #oVECTADDR]
  92        str     r3, [r1, #oVECTADDR]
  93
  94        /* init system clock */
  95        bl system_clock_init
  96
  97#ifndef CONFIG_NAND_SPL
  98        /* for UART */
  99        bl uart_asm_init
 100#endif
 101
 102#ifdef CONFIG_BOOT_NAND
 103        /* simple init for NAND */
 104        bl nand_asm_init
 105#endif
 106
 107        /* Memory subsystem address 0x7e00f120 */
 108        ldr     r0, =ELFIN_MEM_SYS_CFG
 109
 110        /* Xm0CSn2 = NFCON CS0, Xm0CSn3 = NFCON CS1 */
 111        mov     r1, #S3C64XX_MEM_SYS_CFG_NAND
 112        str     r1, [r0]
 113
 114        bl      mem_ctrl_asm_init
 115
 116/* Wakeup support. Don't know if it's going to be used, untested. */
 117        ldr     r0, =(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET)
 118        ldr     r1, [r0]
 119        bic     r1, r1, #0xfffffff7
 120        cmp     r1, #0x8
 121        beq     wakeup_reset
 122
 1231:
 124        mov     lr, r12
 125        mov     pc, lr
 126
 127wakeup_reset:
 128
 129        /* Clear wakeup status register */
 130        ldr     r0, =(ELFIN_CLOCK_POWER_BASE + WAKEUP_STAT_OFFSET)
 131        ldr     r1, [r0]
 132        str     r1, [r0]
 133
 134        /* LED test */
 135        ldr     r0, =ELFIN_GPIO_BASE
 136        ldr     r1, =0x3000
 137        str     r1, [r0, #GPNDAT_OFFSET]
 138
 139        /* Load return address and jump to kernel */
 140        ldr     r0, =(ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET)
 141        /* r1 = physical address of s3c6400_cpu_resume function */
 142        ldr     r1, [r0]
 143        /* Jump to kernel (sleep-s3c6400.S) */
 144        mov     pc, r1
 145        nop
 146        nop
 147/*
 148 * system_clock_init: Initialize core clock and bus clock.
 149 * void system_clock_init(void)
 150 */
 151system_clock_init:
 152        ldr     r0, =ELFIN_CLOCK_POWER_BASE     /* 0x7e00f000 */
 153
 154#ifdef CONFIG_SYNC_MODE
 155        ldr     r1, [r0, #OTHERS_OFFSET]
 156        mov     r2, #0x40
 157        orr     r1, r1, r2
 158        str     r1, [r0, #OTHERS_OFFSET]
 159
 160        nop
 161        nop
 162        nop
 163        nop
 164        nop
 165
 166        ldr     r2, =0x80
 167        orr     r1, r1, r2
 168        str     r1, [r0, #OTHERS_OFFSET]
 169
 170check_syncack:
 171        ldr     r1, [r0, #OTHERS_OFFSET]
 172        ldr     r2, =0xf00
 173        and     r1, r1, r2
 174        cmp     r1, #0xf00
 175        bne     check_syncack
 176#else   /* ASYNC Mode */
 177        nop
 178        nop
 179        nop
 180        nop
 181        nop
 182
 183        /*
 184         * This was unconditional in original Samsung sources, but it doesn't
 185         * seem to make much sense on S3C6400.
 186         */
 187#ifndef CONFIG_S3C6400
 188        ldr     r1, [r0, #OTHERS_OFFSET]
 189        bic     r1, r1, #0xC0
 190        orr     r1, r1, #0x40
 191        str     r1, [r0, #OTHERS_OFFSET]
 192
 193wait_for_async:
 194        ldr     r1, [r0, #OTHERS_OFFSET]
 195        and     r1, r1, #0xf00
 196        cmp     r1, #0x0
 197        bne     wait_for_async
 198#endif
 199
 200        ldr     r1, [r0, #OTHERS_OFFSET]
 201        bic     r1, r1, #0x40
 202        str     r1, [r0, #OTHERS_OFFSET]
 203#endif
 204
 205        mov     r1, #0xff00
 206        orr     r1, r1, #0xff
 207        str     r1, [r0, #APLL_LOCK_OFFSET]
 208        str     r1, [r0, #MPLL_LOCK_OFFSET]
 209
 210        /* Set Clock Divider */
 211        ldr     r1, [r0, #CLK_DIV0_OFFSET]
 212        bic     r1, r1, #0x30000
 213        bic     r1, r1, #0xff00
 214        bic     r1, r1, #0xff
 215        ldr     r2, =CLK_DIV_VAL
 216        orr     r1, r1, r2
 217        str     r1, [r0, #CLK_DIV0_OFFSET]
 218
 219        ldr     r1, =APLL_VAL
 220        str     r1, [r0, #APLL_CON_OFFSET]
 221        ldr     r1, =MPLL_VAL
 222        str     r1, [r0, #MPLL_CON_OFFSET]
 223
 224        /* FOUT of EPLL is 96MHz */
 225        ldr     r1, =0x200203
 226        str     r1, [r0, #EPLL_CON0_OFFSET]
 227        ldr     r1, =0x0
 228        str     r1, [r0, #EPLL_CON1_OFFSET]
 229
 230        /* APLL, MPLL, EPLL select to Fout */
 231        ldr     r1, [r0, #CLK_SRC_OFFSET]
 232        orr     r1, r1, #0x7
 233        str     r1, [r0, #CLK_SRC_OFFSET]
 234
 235        /* wait at least 200us to stablize all clock */
 236        mov     r1, #0x10000
 2371:      subs    r1, r1, #1
 238        bne     1b
 239
 240        /* Synchronization for VIC port */
 241#if defined(CONFIG_SYNC_MODE)
 242        ldr     r1, [r0, #OTHERS_OFFSET]
 243        orr     r1, r1, #0x20
 244        str     r1, [r0, #OTHERS_OFFSET]
 245#elif !defined(CONFIG_S3C6400)
 246        /* According to 661558um_S3C6400X_rev10.pdf 0x20 is reserved */
 247        ldr     r1, [r0, #OTHERS_OFFSET]
 248        bic     r1, r1, #0x20
 249        str     r1, [r0, #OTHERS_OFFSET]
 250#endif
 251        mov     pc, lr
 252
 253
 254#ifndef CONFIG_NAND_SPL
 255/*
 256 * uart_asm_init: Initialize UART's pins
 257 */
 258uart_asm_init:
 259        /* set GPIO to enable UART */
 260        ldr     r0, =ELFIN_GPIO_BASE
 261        ldr     r1, =0x220022
 262        str     r1, [r0, #GPACON_OFFSET]
 263        mov     pc, lr
 264#endif
 265
 266#ifdef CONFIG_BOOT_NAND
 267/*
 268 * NAND Interface init for SMDK6400
 269 */
 270nand_asm_init:
 271        ldr     r0, =ELFIN_NAND_BASE
 272        ldr     r1, [r0, #NFCONF_OFFSET]
 273        orr     r1, r1, #0x70
 274        orr     r1, r1, #0x7700
 275        str     r1, [r0, #NFCONF_OFFSET]
 276
 277        ldr     r1, [r0, #NFCONT_OFFSET]
 278        orr     r1, r1, #0x07
 279        str     r1, [r0, #NFCONT_OFFSET]
 280
 281        mov     pc, lr
 282#endif
 283
 284#ifdef CONFIG_ENABLE_MMU
 285/*
 286 * MMU Table for SMDK6400
 287 */
 288
 289        /* form a first-level section entry */
 290.macro FL_SECTION_ENTRY base,ap,d,c,b
 291        .word (\base << 20) | (\ap << 10) | \
 292              (\d << 5) | (1<<4) | (\c << 3) | (\b << 2) | (1<<1)
 293.endm
 294
 295.section .mmudata, "a"
 296        .align 14
 297        /* the following alignment creates the mmu table at address 0x4000. */
 298        .globl mmu_table
 299mmu_table:
 300        .set __base, 0
 301        /* 1:1 mapping for debugging */
 302        .rept 0xA00
 303        FL_SECTION_ENTRY __base, 3, 0, 0, 0
 304        .set __base, __base + 1
 305        .endr
 306
 307        /* access is not allowed. */
 308        .rept 0xC00 - 0xA00
 309        .word 0x00000000
 310        .endr
 311
 312        /* 128MB for SDRAM 0xC0000000 -> 0x50000000 */
 313        .set __base, 0x500
 314        .rept 0xC80 - 0xC00
 315        FL_SECTION_ENTRY __base, 3, 0, 1, 1
 316        .set __base, __base + 1
 317        .endr
 318
 319        /* access is not allowed. */
 320        .rept 0x1000 - 0xc80
 321        .word 0x00000000
 322        .endr
 323#endif
 324