1/* 2 * (C) Copyright 2004-2010 3 * Texas Instruments, <www.ti.com> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23#ifndef _OMAP2PLUS_I2C_H_ 24#define _OMAP2PLUS_I2C_H_ 25 26/* I2C masks */ 27 28/* I2C Interrupt Enable Register (I2C_IE): */ 29#define I2C_IE_GC_IE (1 << 5) 30#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ 31#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ 32#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ 33#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ 34#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ 35 36/* I2C Status Register (I2C_STAT): */ 37 38#define I2C_STAT_SBD (1 << 15) /* Single byte data */ 39#define I2C_STAT_BB (1 << 12) /* Bus busy */ 40#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ 41#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ 42#define I2C_STAT_AAS (1 << 9) /* Address as slave */ 43#define I2C_STAT_GC (1 << 5) 44#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ 45#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ 46#define I2C_STAT_ARDY (1 << 2) /* Register access ready */ 47#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ 48#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ 49 50/* I2C Interrupt Code Register (I2C_INTCODE): */ 51 52#define I2C_INTCODE_MASK 7 53#define I2C_INTCODE_NONE 0 54#define I2C_INTCODE_AL 1 /* Arbitration lost */ 55#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */ 56#define I2C_INTCODE_ARDY 3 /* Register access ready */ 57#define I2C_INTCODE_RRDY 4 /* Rcv data ready */ 58#define I2C_INTCODE_XRDY 5 /* Xmit data ready */ 59 60/* I2C Buffer Configuration Register (I2C_BUF): */ 61 62#define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */ 63#define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */ 64 65/* I2C Configuration Register (I2C_CON): */ 66 67#define I2C_CON_EN (1 << 15) /* I2C module enable */ 68#define I2C_CON_BE (1 << 14) /* Big endian mode */ 69#define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */ 70#define I2C_CON_MST (1 << 10) /* Master/slave mode */ 71#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode */ 72 /* (master mode only) */ 73#define I2C_CON_XA (1 << 8) /* Expand address */ 74#define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */ 75#define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */ 76 77/* I2C System Test Register (I2C_SYSTEST): */ 78 79#define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ 80#define I2C_SYSTEST_FREE (1 << 14) /* Free running mode, on brkpoint) */ 81#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ 82#define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ 83#define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */ 84#define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */ 85#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */ 86#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */ 87 88/* I2C System Status Register (I2C_SYSS): */ 89 90#define I2C_SYSS_RDONE (1 << 0) /* Internel reset monitoring */ 91 92#define I2C_SCLL_SCLL 0 93#define I2C_SCLL_SCLL_M 0xFF 94#define I2C_SCLL_HSSCLL 8 95#define I2C_SCLH_HSSCLL_M 0xFF 96#define I2C_SCLH_SCLH 0 97#define I2C_SCLH_SCLH_M 0xFF 98#define I2C_SCLH_HSSCLH 8 99#define I2C_SCLH_HSSCLH_M 0xFF 100 101#define OMAP_I2C_STANDARD 100000 102#define OMAP_I2C_FAST_MODE 400000 103#define OMAP_I2C_HIGH_SPEED 3400000 104 105#define SYSTEM_CLOCK_12 12000000 106#define SYSTEM_CLOCK_13 13000000 107#define SYSTEM_CLOCK_192 19200000 108#define SYSTEM_CLOCK_96 96000000 109 110/* Use the reference value of 96MHz if not explicitly set by the board */ 111#ifndef I2C_IP_CLK 112#define I2C_IP_CLK SYSTEM_CLOCK_96 113#endif 114 115/* 116 * The reference minimum clock for high speed is 19.2MHz. 117 * The linux 2.6.30 kernel uses this value. 118 * The reference minimum clock for fast mode is 9.6MHz 119 * The reference minimum clock for standard mode is 4MHz 120 * In TRM, the value of 12MHz is used. 121 */ 122#ifndef I2C_INTERNAL_SAMPLING_CLK 123#define I2C_INTERNAL_SAMPLING_CLK 19200000 124#endif 125 126/* 127 * The equation for the low and high time is 128 * tlow = scll + scll_trim = (sampling clock * tlow_duty) / speed 129 * thigh = sclh + sclh_trim = (sampling clock * (1 - tlow_duty)) / speed 130 * 131 * If the duty cycle is 50% 132 * 133 * tlow = scll + scll_trim = sampling clock / (2 * speed) 134 * thigh = sclh + sclh_trim = sampling clock / (2 * speed) 135 * 136 * In TRM 137 * scll_trim = 7 138 * sclh_trim = 5 139 * 140 * The linux 2.6.30 kernel uses 141 * scll_trim = 6 142 * sclh_trim = 6 143 * 144 * These are the trim values for standard and fast speed 145 */ 146#ifndef I2C_FASTSPEED_SCLL_TRIM 147#define I2C_FASTSPEED_SCLL_TRIM 6 148#endif 149#ifndef I2C_FASTSPEED_SCLH_TRIM 150#define I2C_FASTSPEED_SCLH_TRIM 6 151#endif 152 153/* These are the trim values for high speed */ 154#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM 155#define I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM 156#endif 157#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM 158#define I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM 159#endif 160#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM 161#define I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM 162#endif 163#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM 164#define I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM 165#endif 166 167#define I2C_PSC_MAX 0x0f 168#define I2C_PSC_MIN 0x00 169 170#endif /* _OMAP24XX_I2C_H_ */ 171