LXR uboot/drivers/i2c/sh_sh7734

   1/*
   2 * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
   3 * Copyright (C) 2012 Renesas Solutions Corp.
   4 *
   5 * This program is free software; you can redistribute it and/or
   6 * modify it under the terms of the GNU General Public License as
   7 * published by the Free Software Foundation; either version 2 of
   8 * the License, or (at your option) any later version.
   9 *
  10 * This program is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 * GNU General Public License for more details.
  14 *
  15 * You should have received a copy of the GNU General Public License
  16 * along with this program; if not, write to the Free Software
  17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18 * MA 02111-1307 USA
  19 */
  20
  21#include <common.h>
  22#include <i2c.h>
  23#include <asm/io.h>
  24
  25struct sh_i2c {
  26        u8 iccr1;
  27        u8 iccr2;
  28        u8 icmr;
  29        u8 icier;
  30        u8 icsr;
  31        u8 sar;
  32        u8 icdrt;
  33        u8 icdrr;
  34        u8 nf2cyc;
  35        u8 __pad0;
  36        u8 __pad1;
  37};
  38
  39static struct sh_i2c *base;
  40static u8 iccr1_cks, nf2cyc;
  41
  42/* ICCR1 */
  43#define SH_I2C_ICCR1_ICE        (1 << 7)
  44#define SH_I2C_ICCR1_RCVD       (1 << 6)
  45#define SH_I2C_ICCR1_MST        (1 << 5)
  46#define SH_I2C_ICCR1_TRS        (1 << 4)
  47#define SH_I2C_ICCR1_MTRS       \
  48        (SH_I2C_ICCR1_MST | SH_I2C_ICCR1_TRS)
  49
  50/* ICCR1 */
  51#define SH_I2C_ICCR2_BBSY       (1 << 7)
  52#define SH_I2C_ICCR2_SCP        (1 << 6)
  53#define SH_I2C_ICCR2_SDAO       (1 << 5)
  54#define SH_I2C_ICCR2_SDAOP      (1 << 4)
  55#define SH_I2C_ICCR2_SCLO       (1 << 3)
  56#define SH_I2C_ICCR2_IICRST     (1 << 1)
  57
  58#define SH_I2C_ICIER_TIE        (1 << 7)
  59#define SH_I2C_ICIER_TEIE       (1 << 6)
  60#define SH_I2C_ICIER_RIE        (1 << 5)
  61#define SH_I2C_ICIER_NAKIE      (1 << 4)
  62#define SH_I2C_ICIER_STIE       (1 << 3)
  63#define SH_I2C_ICIER_ACKE       (1 << 2)
  64#define SH_I2C_ICIER_ACKBR      (1 << 1)
  65#define SH_I2C_ICIER_ACKBT      (1 << 0)
  66
  67#define SH_I2C_ICSR_TDRE        (1 << 7)
  68#define SH_I2C_ICSR_TEND        (1 << 6)
  69#define SH_I2C_ICSR_RDRF        (1 << 5)
  70#define SH_I2C_ICSR_NACKF       (1 << 4)
  71#define SH_I2C_ICSR_STOP        (1 << 3)
  72#define SH_I2C_ICSR_ALOVE       (1 << 2)
  73#define SH_I2C_ICSR_AAS         (1 << 1)
  74#define SH_I2C_ICSR_ADZ         (1 << 0)
  75
  76#define IRQ_WAIT 1000
  77
  78static void sh_i2c_send_stop(struct sh_i2c *base)
  79{
  80        clrbits_8(&base->iccr2, SH_I2C_ICCR2_BBSY | SH_I2C_ICCR2_SCP);
  81}
  82
  83static int check_icsr_bits(struct sh_i2c *base, u8 bits)
  84{
  85        int i;
  86
  87        for (i = 0; i < IRQ_WAIT; i++) {
  88                if (bits & readb(&base->icsr))
  89                        return 0;
  90                udelay(10);
  91        }
  92
  93        return 1;
  94}
  95
  96static int check_stop(struct sh_i2c *base)
  97{
  98        int ret = check_icsr_bits(base, SH_I2C_ICSR_STOP);
  99        clrbits_8(&base->icsr, SH_I2C_ICSR_STOP);
 100
 101        return ret;
 102}
 103
 104static int check_tend(struct sh_i2c *base, int stop)
 105{
 106        int ret = check_icsr_bits(base, SH_I2C_ICSR_TEND);
 107
 108        if (stop) {
 109                clrbits_8(&base->icsr, SH_I2C_ICSR_STOP);
 110                sh_i2c_send_stop(base);
 111        }
 112
 113        clrbits_8(&base->icsr, SH_I2C_ICSR_TEND);
 114        return ret;
 115}
 116
 117static int check_tdre(struct sh_i2c *base)
 118{
 119        return check_icsr_bits(base, SH_I2C_ICSR_TDRE);
 120}
 121
 122static int check_rdrf(struct sh_i2c *base)
 123{
 124        return check_icsr_bits(base, SH_I2C_ICSR_RDRF);
 125}
 126
 127static int check_bbsy(struct sh_i2c *base)
 128{
 129        int i;
 130
 131        for (i = 0 ; i < IRQ_WAIT ; i++) {
 132                if (!(SH_I2C_ICCR2_BBSY & readb(&base->iccr2)))
 133                        return 0;
 134                udelay(10);
 135        }
 136        return 1;
 137}
 138
 139static int check_ackbr(struct sh_i2c *base)
 140{
 141        int i;
 142
 143        for (i = 0 ; i < IRQ_WAIT ; i++) {
 144                if (!(SH_I2C_ICIER_ACKBR & readb(&base->icier)))
 145                        return 0;
 146                udelay(10);
 147        }
 148
 149        return 1;
 150}
 151
 152static void sh_i2c_reset(struct sh_i2c *base)
 153{
 154        setbits_8(&base->iccr2, SH_I2C_ICCR2_IICRST);
 155
 156        udelay(100);
 157
 158        clrbits_8(&base->iccr2, SH_I2C_ICCR2_IICRST);
 159}
 160
 161static int i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg)
 162{
 163        if (check_bbsy(base)) {
 164                puts("i2c bus busy\n");
 165                goto fail;
 166        }
 167
 168        setbits_8(&base->iccr1, SH_I2C_ICCR1_MTRS);
 169        clrsetbits_8(&base->iccr2, SH_I2C_ICCR2_SCP, SH_I2C_ICCR2_BBSY);
 170
 171        writeb((id << 1), &base->icdrt);
 172
 173        if (check_tend(base, 0)) {
 174                puts("TEND check fail...\n");
 175                goto fail;
 176        }
 177
 178        if (check_ackbr(base)) {
 179                check_tend(base, 0);
 180                sh_i2c_send_stop(base);
 181                goto fail;
 182        }
 183
 184        writeb(reg, &base->icdrt);
 185
 186        if (check_tdre(base)) {
 187                puts("TDRE check fail...\n");
 188                goto fail;
 189        }
 190
 191        if (check_tend(base, 0)) {
 192                puts("TEND check fail...\n");
 193                goto fail;
 194        }
 195
 196        return 0;
 197fail:
 198
 199        return 1;
 200}
 201
 202static int
 203i2c_raw_write(struct sh_i2c *base, u8 id, u8 reg, u8 *val, int size)
 204{
 205        int i;
 206
 207        if (i2c_set_addr(base, id, reg)) {
 208                puts("Fail set slave address\n");
 209                return 1;
 210        }
 211
 212        for (i = 0; i < size; i++) {
 213                writeb(val[i], &base->icdrt);
 214                check_tdre(base);
 215        }
 216
 217        check_tend(base, 1);
 218        check_stop(base);
 219
 220        udelay(100);
 221
 222        clrbits_8(&base->iccr1, SH_I2C_ICCR1_MTRS);
 223        clrbits_8(&base->icsr, SH_I2C_ICSR_TDRE);
 224        sh_i2c_reset(base);
 225
 226        return 0;
 227}
 228
 229static u8 i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg)
 230{
 231        u8 ret = 0;
 232
 233        if (i2c_set_addr(base, id, reg)) {
 234                puts("Fail set slave address\n");
 235                goto fail;
 236        }
 237
 238        clrsetbits_8(&base->iccr2, SH_I2C_ICCR2_SCP, SH_I2C_ICCR2_BBSY);
 239        writeb((id << 1) | 1, &base->icdrt);
 240
 241        if (check_tend(base, 0))
 242                puts("TDRE check fail...\n");
 243
 244        clrsetbits_8(&base->iccr1, SH_I2C_ICCR1_TRS, SH_I2C_ICCR1_MST);
 245        clrbits_8(&base->icsr, SH_I2C_ICSR_TDRE);
 246        setbits_8(&base->icier, SH_I2C_ICIER_ACKBT);
 247        setbits_8(&base->iccr1, SH_I2C_ICCR1_RCVD);
 248
 249        /* read data (dummy) */
 250        ret = readb(&base->icdrr);
 251
 252        if (check_rdrf(base)) {
 253                puts("check RDRF error\n");
 254                goto fail;
 255        }
 256
 257        clrbits_8(&base->icsr, SH_I2C_ICSR_STOP);
 258        udelay(1000);
 259
 260        sh_i2c_send_stop(base);
 261
 262        if (check_stop(base)) {
 263                puts("check STOP error\n");
 264                goto fail;
 265        }
 266
 267        clrbits_8(&base->iccr1, SH_I2C_ICCR1_MTRS);
 268        clrbits_8(&base->icsr, SH_I2C_ICSR_TDRE);
 269
 270        /* data read */
 271        ret = readb(&base->icdrr);
 272
 273fail:
 274        clrbits_8(&base->iccr1, SH_I2C_ICCR1_RCVD);
 275
 276        return ret;
 277}
 278
 279#ifdef CONFIG_I2C_MULTI_BUS
 280static unsigned int current_bus;
 281
 282/**
 283 * i2c_set_bus_num - change active I2C bus
 284 *      @bus: bus index, zero based
 285 *      @returns: 0 on success, non-0 on failure
 286 */
 287int i2c_set_bus_num(unsigned int bus)
 288{
 289        switch (bus) {
 290        case 0:
 291                base = (void *)CONFIG_SH_I2C_BASE0;
 292                break;
 293        case 1:
 294                base = (void *)CONFIG_SH_I2C_BASE1;
 295                break;
 296        default:
 297                printf("Bad bus: %d\n", bus);
 298                return -1;
 299        }
 300
 301        current_bus = bus;
 302
 303        return 0;
 304}
 305
 306/**
 307 * i2c_get_bus_num - returns index of active I2C bus
 308 */
 309unsigned int i2c_get_bus_num(void)
 310{
 311        return current_bus;
 312}
 313#endif
 314
 315void i2c_init(int speed, int slaveaddr)
 316{
 317#ifdef CONFIG_I2C_MULTI_BUS
 318        current_bus = 0;
 319#endif
 320        base = (struct sh_i2c *)CONFIG_SH_I2C_BASE0;
 321
 322        if (speed == 400000)
 323                iccr1_cks = 0x07;
 324        else
 325                iccr1_cks = 0x0F;
 326
 327        nf2cyc = 1;
 328
 329        /* Reset */
 330        sh_i2c_reset(base);
 331
 332        /* ICE enable and set clock */
 333        writeb(SH_I2C_ICCR1_ICE | iccr1_cks, &base->iccr1);
 334        writeb(nf2cyc, &base->nf2cyc);
 335}
 336
 337/*
 338 * i2c_read: - Read multiple bytes from an i2c device
 339 *
 340 * The higher level routines take into account that this function is only
 341 * called with len < page length of the device (see configuration file)
 342 *
 343 * @chip:   address of the chip which is to be read
 344 * @addr:   i2c data address within the chip
 345 * @alen:   length of the i2c data address (1..2 bytes)
 346 * @buffer: where to write the data
 347 * @len:    how much byte do we want to read
 348 * @return: 0 in case of success
 349 */
 350int i2c_read(u8 chip, u32 addr, int alen, u8 *buffer, int len)
 351{
 352        int i = 0;
 353        for (i = 0; i < len; i++)
 354                buffer[i] = i2c_raw_read(base, chip, addr + i);
 355
 356        return 0;
 357}
 358
 359/*
 360 * i2c_write: -  Write multiple bytes to an i2c device
 361 *
 362 * The higher level routines take into account that this function is only
 363 * called with len < page length of the device (see configuration file)
 364 *
 365 * @chip:   address of the chip which is to be written
 366 * @addr:   i2c data address within the chip
 367 * @alen:   length of the i2c data address (1..2 bytes)
 368 * @buffer: where to find the data to be written
 369 * @len:    how much byte do we want to read
 370 * @return: 0 in case of success
 371 */
 372int i2c_write(u8 chip, u32 addr, int alen, u8 *buffer, int len)
 373{
 374        return i2c_raw_write(base, chip, addr, buffer, len);
 375}
 376
 377/*
 378 * i2c_probe: - Test if a chip answers for a given i2c address
 379 *
 380 * @chip:   address of the chip which is searched for
 381 * @return: 0 if a chip was found, -1 otherwhise
 382 */
 383int i2c_probe(u8 chip)
 384{
 385        u8 byte;
 386        return i2c_read(chip, 0, 0, &byte, 1);
 387}
 388