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19#include <config.h>
20#include <common.h>
21#include <command.h>
22#include <mmc.h>
23#include <part.h>
24#include <malloc.h>
25#include <mmc.h>
26#include <asm/errno.h>
27#include <asm/io.h>
28#include <asm/arch/clock.h>
29
30#define DRIVER_NAME "mxc-mmc"
31
32struct mxcmci_regs {
33 u32 str_stp_clk;
34 u32 status;
35 u32 clk_rate;
36 u32 cmd_dat_cont;
37 u32 res_to;
38 u32 read_to;
39 u32 blk_len;
40 u32 nob;
41 u32 rev_no;
42 u32 int_cntr;
43 u32 cmd;
44 u32 arg;
45 u32 pad;
46 u32 res_fifo;
47 u32 buffer_access;
48};
49
50#define STR_STP_CLK_RESET (1 << 3)
51#define STR_STP_CLK_START_CLK (1 << 1)
52#define STR_STP_CLK_STOP_CLK (1 << 0)
53
54#define STATUS_CARD_INSERTION (1 << 31)
55#define STATUS_CARD_REMOVAL (1 << 30)
56#define STATUS_YBUF_EMPTY (1 << 29)
57#define STATUS_XBUF_EMPTY (1 << 28)
58#define STATUS_YBUF_FULL (1 << 27)
59#define STATUS_XBUF_FULL (1 << 26)
60#define STATUS_BUF_UND_RUN (1 << 25)
61#define STATUS_BUF_OVFL (1 << 24)
62#define STATUS_SDIO_INT_ACTIVE (1 << 14)
63#define STATUS_END_CMD_RESP (1 << 13)
64#define STATUS_WRITE_OP_DONE (1 << 12)
65#define STATUS_DATA_TRANS_DONE (1 << 11)
66#define STATUS_READ_OP_DONE (1 << 11)
67#define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10)
68#define STATUS_CARD_BUS_CLK_RUN (1 << 8)
69#define STATUS_BUF_READ_RDY (1 << 7)
70#define STATUS_BUF_WRITE_RDY (1 << 6)
71#define STATUS_RESP_CRC_ERR (1 << 5)
72#define STATUS_CRC_READ_ERR (1 << 3)
73#define STATUS_CRC_WRITE_ERR (1 << 2)
74#define STATUS_TIME_OUT_RESP (1 << 1)
75#define STATUS_TIME_OUT_READ (1 << 0)
76#define STATUS_ERR_MASK 0x2f
77
78#define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12)
79#define CMD_DAT_CONT_STOP_READWAIT (1 << 11)
80#define CMD_DAT_CONT_START_READWAIT (1 << 10)
81#define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8)
82#define CMD_DAT_CONT_INIT (1 << 7)
83#define CMD_DAT_CONT_WRITE (1 << 4)
84#define CMD_DAT_CONT_DATA_ENABLE (1 << 3)
85#define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0)
86#define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0)
87#define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0)
88
89#define INT_SDIO_INT_WKP_EN (1 << 18)
90#define INT_CARD_INSERTION_WKP_EN (1 << 17)
91#define INT_CARD_REMOVAL_WKP_EN (1 << 16)
92#define INT_CARD_INSERTION_EN (1 << 15)
93#define INT_CARD_REMOVAL_EN (1 << 14)
94#define INT_SDIO_IRQ_EN (1 << 13)
95#define INT_DAT0_EN (1 << 12)
96#define INT_BUF_READ_EN (1 << 4)
97#define INT_BUF_WRITE_EN (1 << 3)
98#define INT_END_CMD_RES_EN (1 << 2)
99#define INT_WRITE_OP_DONE_EN (1 << 1)
100#define INT_READ_OP_EN (1 << 0)
101
102struct mxcmci_host {
103 struct mmc *mmc;
104 struct mxcmci_regs *base;
105 int irq;
106 int detect_irq;
107 int dma;
108 int do_dma;
109 unsigned int power_mode;
110
111 struct mmc_cmd *cmd;
112 struct mmc_data *data;
113
114 unsigned int dma_nents;
115 unsigned int datasize;
116 unsigned int dma_dir;
117
118 u16 rev_no;
119 unsigned int cmdat;
120
121 int clock;
122};
123
124static struct mxcmci_host mxcmci_host;
125static struct mxcmci_host *host = &mxcmci_host;
126
127static inline int mxcmci_use_dma(struct mxcmci_host *host)
128{
129 return host->do_dma;
130}
131
132static void mxcmci_softreset(struct mxcmci_host *host)
133{
134 int i;
135
136
137 writel(STR_STP_CLK_RESET, &host->base->str_stp_clk);
138 writel(STR_STP_CLK_RESET | STR_STP_CLK_START_CLK,
139 &host->base->str_stp_clk);
140
141 for (i = 0; i < 8; i++)
142 writel(STR_STP_CLK_START_CLK, &host->base->str_stp_clk);
143
144 writel(0xff, &host->base->res_to);
145}
146
147static void mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data)
148{
149 unsigned int nob = data->blocks;
150 unsigned int blksz = data->blocksize;
151 unsigned int datasize = nob * blksz;
152
153 host->data = data;
154
155 writel(nob, &host->base->nob);
156 writel(blksz, &host->base->blk_len);
157 host->datasize = datasize;
158}
159
160static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_cmd *cmd,
161 unsigned int cmdat)
162{
163 if (host->cmd != NULL)
164 printf("mxcmci: error!\n");
165 host->cmd = cmd;
166
167 switch (cmd->resp_type) {
168 case MMC_RSP_R1:
169 case MMC_RSP_R1b:
170 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT_CRC;
171 break;
172 case MMC_RSP_R2:
173 cmdat |= CMD_DAT_CONT_RESPONSE_136BIT;
174 break;
175 case MMC_RSP_R3:
176 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT;
177 break;
178 case MMC_RSP_NONE:
179 break;
180 default:
181 printf("mxcmci: unhandled response type 0x%x\n",
182 cmd->resp_type);
183 return -EINVAL;
184 }
185
186 writel(cmd->cmdidx, &host->base->cmd);
187 writel(cmd->cmdarg, &host->base->arg);
188 writel(cmdat, &host->base->cmd_dat_cont);
189
190 return 0;
191}
192
193static void mxcmci_finish_request(struct mxcmci_host *host,
194 struct mmc_cmd *cmd, struct mmc_data *data)
195{
196 host->cmd = NULL;
197 host->data = NULL;
198}
199
200static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat)
201{
202 int data_error = 0;
203
204 if (stat & STATUS_ERR_MASK) {
205 printf("request failed. status: 0x%08x\n",
206 stat);
207 if (stat & STATUS_CRC_READ_ERR) {
208 data_error = -EILSEQ;
209 } else if (stat & STATUS_CRC_WRITE_ERR) {
210 u32 err_code = (stat >> 9) & 0x3;
211 if (err_code == 2)
212 data_error = TIMEOUT;
213 else
214 data_error = -EILSEQ;
215 } else if (stat & STATUS_TIME_OUT_READ) {
216 data_error = TIMEOUT;
217 } else {
218 data_error = -EIO;
219 }
220 }
221
222 host->data = NULL;
223
224 return data_error;
225}
226
227static int mxcmci_read_response(struct mxcmci_host *host, unsigned int stat)
228{
229 struct mmc_cmd *cmd = host->cmd;
230 int i;
231 u32 a, b, c;
232 u32 *resp = (u32 *)cmd->response;
233
234 if (!cmd)
235 return 0;
236
237 if (stat & STATUS_TIME_OUT_RESP) {
238 printf("CMD TIMEOUT\n");
239 return TIMEOUT;
240 } else if (stat & STATUS_RESP_CRC_ERR && cmd->resp_type & MMC_RSP_CRC) {
241 printf("cmd crc error\n");
242 return -EILSEQ;
243 }
244
245 if (cmd->resp_type & MMC_RSP_PRESENT) {
246 if (cmd->resp_type & MMC_RSP_136) {
247 for (i = 0; i < 4; i++) {
248 a = readl(&host->base->res_fifo) & 0xFFFF;
249 b = readl(&host->base->res_fifo) & 0xFFFF;
250 resp[i] = a << 16 | b;
251 }
252 } else {
253 a = readl(&host->base->res_fifo) & 0xFFFF;
254 b = readl(&host->base->res_fifo) & 0xFFFF;
255 c = readl(&host->base->res_fifo) & 0xFFFF;
256 resp[0] = a << 24 | b << 8 | c >> 8;
257 }
258 }
259 return 0;
260}
261
262static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask)
263{
264 u32 stat;
265 unsigned long timeout = get_ticks() + CONFIG_SYS_HZ;
266
267 do {
268 stat = readl(&host->base->status);
269 if (stat & STATUS_ERR_MASK)
270 return stat;
271 if (timeout < get_ticks())
272 return STATUS_TIME_OUT_READ;
273 if (stat & mask)
274 return 0;
275 } while (1);
276}
277
278static int mxcmci_pull(struct mxcmci_host *host, void *_buf, int bytes)
279{
280 unsigned int stat;
281 u32 *buf = _buf;
282
283 while (bytes > 3) {
284 stat = mxcmci_poll_status(host,
285 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
286 if (stat)
287 return stat;
288 *buf++ = readl(&host->base->buffer_access);
289 bytes -= 4;
290 }
291
292 if (bytes) {
293 u8 *b = (u8 *)buf;
294 u32 tmp;
295
296 stat = mxcmci_poll_status(host,
297 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
298 if (stat)
299 return stat;
300 tmp = readl(&host->base->buffer_access);
301 memcpy(b, &tmp, bytes);
302 }
303
304 return 0;
305}
306
307static int mxcmci_push(struct mxcmci_host *host, const void *_buf, int bytes)
308{
309 unsigned int stat;
310 const u32 *buf = _buf;
311
312 while (bytes > 3) {
313 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
314 if (stat)
315 return stat;
316 writel(*buf++, &host->base->buffer_access);
317 bytes -= 4;
318 }
319
320 if (bytes) {
321 const u8 *b = (u8 *)buf;
322 u32 tmp;
323
324 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
325 if (stat)
326 return stat;
327
328 memcpy(&tmp, b, bytes);
329 writel(tmp, &host->base->buffer_access);
330 }
331
332 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
333 if (stat)
334 return stat;
335
336 return 0;
337}
338
339static int mxcmci_transfer_data(struct mxcmci_host *host)
340{
341 struct mmc_data *data = host->data;
342 int stat;
343 unsigned long length;
344
345 length = data->blocks * data->blocksize;
346 host->datasize = 0;
347
348 if (data->flags & MMC_DATA_READ) {
349 stat = mxcmci_pull(host, data->dest, length);
350 if (stat)
351 return stat;
352 host->datasize += length;
353 } else {
354 stat = mxcmci_push(host, (const void *)(data->src), length);
355 if (stat)
356 return stat;
357 host->datasize += length;
358 stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE);
359 if (stat)
360 return stat;
361 }
362 return 0;
363}
364
365static int mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat)
366{
367 int datastat;
368 int ret;
369
370 ret = mxcmci_read_response(host, stat);
371
372 if (ret) {
373 mxcmci_finish_request(host, host->cmd, host->data);
374 return ret;
375 }
376
377 if (!host->data) {
378 mxcmci_finish_request(host, host->cmd, host->data);
379 return 0;
380 }
381
382 datastat = mxcmci_transfer_data(host);
383 ret = mxcmci_finish_data(host, datastat);
384 mxcmci_finish_request(host, host->cmd, host->data);
385 return ret;
386}
387
388static int mxcmci_request(struct mmc *mmc, struct mmc_cmd *cmd,
389 struct mmc_data *data)
390{
391 struct mxcmci_host *host = mmc->priv;
392 unsigned int cmdat = host->cmdat;
393 u32 stat;
394 int ret;
395
396 host->cmdat &= ~CMD_DAT_CONT_INIT;
397 if (data) {
398 mxcmci_setup_data(host, data);
399
400 cmdat |= CMD_DAT_CONT_DATA_ENABLE;
401
402 if (data->flags & MMC_DATA_WRITE)
403 cmdat |= CMD_DAT_CONT_WRITE;
404 }
405
406 if ((ret = mxcmci_start_cmd(host, cmd, cmdat))) {
407 mxcmci_finish_request(host, cmd, data);
408 return ret;
409 }
410
411 do {
412 stat = readl(&host->base->status);
413 writel(stat, &host->base->status);
414 } while (!(stat & STATUS_END_CMD_RESP));
415
416 return mxcmci_cmd_done(host, stat);
417}
418
419static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios)
420{
421 unsigned int divider;
422 int prescaler = 0;
423 unsigned long clk_in = mxc_get_clock(MXC_ESDHC_CLK);
424
425 while (prescaler <= 0x800) {
426 for (divider = 1; divider <= 0xF; divider++) {
427 int x;
428
429 x = (clk_in / (divider + 1));
430
431 if (prescaler)
432 x /= (prescaler * 2);
433
434 if (x <= clk_ios)
435 break;
436 }
437 if (divider < 0x10)
438 break;
439
440 if (prescaler == 0)
441 prescaler = 1;
442 else
443 prescaler <<= 1;
444 }
445
446 writel((prescaler << 4) | divider, &host->base->clk_rate);
447}
448
449static void mxcmci_set_ios(struct mmc *mmc)
450{
451 struct mxcmci_host *host = mmc->priv;
452 if (mmc->bus_width == 4)
453 host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
454 else
455 host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4;
456
457 if (mmc->clock) {
458 mxcmci_set_clk_rate(host, mmc->clock);
459 writel(STR_STP_CLK_START_CLK, &host->base->str_stp_clk);
460 } else {
461 writel(STR_STP_CLK_STOP_CLK, &host->base->str_stp_clk);
462 }
463
464 host->clock = mmc->clock;
465}
466
467static int mxcmci_init(struct mmc *mmc)
468{
469 struct mxcmci_host *host = mmc->priv;
470
471 mxcmci_softreset(host);
472
473 host->rev_no = readl(&host->base->rev_no);
474 if (host->rev_no != 0x400) {
475 printf("wrong rev.no. 0x%08x. aborting.\n",
476 host->rev_no);
477 return -ENODEV;
478 }
479
480
481 writel(0x2db4, &host->base->read_to);
482
483 writel(0, &host->base->int_cntr);
484
485 return 0;
486}
487
488static int mxcmci_initialize(bd_t *bis)
489{
490 struct mmc *mmc = NULL;
491
492 mmc = malloc(sizeof(struct mmc));
493
494 if (!mmc)
495 return -ENOMEM;
496
497 sprintf(mmc->name, "MXC MCI");
498 mmc->send_cmd = mxcmci_request;
499 mmc->set_ios = mxcmci_set_ios;
500 mmc->init = mxcmci_init;
501 mmc->getcd = NULL;
502 mmc->host_caps = MMC_MODE_4BIT;
503
504 host->base = (struct mxcmci_regs *)CONFIG_MXC_MCI_REGS_BASE;
505 mmc->priv = host;
506 host->mmc = mmc;
507
508 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
509
510 mmc->f_min = mxc_get_clock(MXC_ESDHC_CLK) >> 7;
511 mmc->f_max = mxc_get_clock(MXC_ESDHC_CLK) >> 1;
512
513 mmc->b_max = 0;
514
515 mmc_register(mmc);
516
517 return 0;
518}
519
520int mxc_mmc_init(bd_t *bis)
521{
522 return mxcmci_initialize(bis);
523}
524
