1/* 2 * (C) Copyright 2001 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* 25 * 26 * Configuration settings for the CU824 board. 27 * 28 */ 29 30/* ------------------------------------------------------------------------- */ 31 32/* 33 * board/config.h - configuration options, board specific 34 */ 35 36#ifndef __CONFIG_H 37#define __CONFIG_H 38 39/* 40 * High Level Configuration Options 41 * (easy to change) 42 */ 43 44#define CONFIG_MPC824X 1 45#define CONFIG_MPC8245 1 46#define CONFIG_BMW 1 47 48#define CONFIG_SYS_TEXT_BASE 0xFFF00000 49 50#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ 51 52#define CONFIG_CONS_INDEX 1 53#define CONFIG_BAUDRATE 9600 54 55#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ 56 57#define CONFIG_BOOTCOMMAND "bootm FF820000" /* autoboot command */ 58#define CONFIG_BOOTDELAY 5 59 60#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Only use Onboard TSOP-16MB device */ 61#define DOC_PASSIVE_PROBE 1 62#define CONFIG_SYS_DOC_SUPPORT_2000 1 63#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM 1 64#define CONFIG_SYS_DOC_SHORT_TIMEOUT 1 65 66 67/* 68 * BOOTP options 69 */ 70#define CONFIG_BOOTP_BOOTFILESIZE 71#define CONFIG_BOOTP_BOOTPATH 72#define CONFIG_BOOTP_GATEWAY 73#define CONFIG_BOOTP_HOSTNAME 74 75 76/* 77 * Command line configuration. 78 */ 79#include <config_cmd_default.h> 80 81#define CONFIG_CMD_DATE 82#define CONFIG_CMD_ELF 83#undef CONFIG_CMD_NET 84#undef CONFIG_CMD_NFS 85 86 87#if 0 88#define CONFIG_PCI 1 89#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */ 90#endif 91 92/* 93 * Miscellaneous configurable options 94 */ 95#define CONFIG_SYS_LONGHELP /* undef to save memory */ 96#define CONFIG_SYS_PROMPT "=>" /* Monitor Command Prompt */ 97#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 98 99/* Print Buffer Size 100 */ 101#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 102 103#define CONFIG_SYS_MAXARGS 8 /* Max number of command args */ 104#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 105#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */ 106 107/*----------------------------------------------------------------------- 108 * Start addresses for the final memory configuration 109 * (Set up by the startup code) 110 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 111 */ 112#define CONFIG_SYS_SDRAM_BASE 0x00000000 113 114#define CONFIG_SYS_FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank on RCS#0 */ 115#define CONFIG_SYS_FLASH_BASE1_PRELIM 0xFF800000 /* FLASH bank on RCS#1 */ 116#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE 117#define CONFIG_SYS_FLASH_BANKS { CONFIG_SYS_FLASH_BASE0_PRELIM , CONFIG_SYS_FLASH_BASE1_PRELIM } 118 119/* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the 120 * reset vector is actually located at FFB00100, but the 8245 121 * takes care of us. 122 */ 123#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 124 125#define CONFIG_SYS_EUMB_ADDR 0xFC000000 126 127#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 128 129#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 130#define CONFIG_SYS_MALLOC_LEN (2048 << 10) /* Reserve 2MB for malloc() */ 131 132#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ 133#define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */ 134 135 /* Maximum amount of RAM. 136 */ 137#define CONFIG_SYS_MAX_RAM_SIZE 0x04000000 /* 0 .. 64 MB of (S)DRAM */ 138 139 140#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE 141#undef CONFIG_SYS_RAMBOOT 142#else 143#define CONFIG_SYS_RAMBOOT 144#endif 145 146 147/*----------------------------------------------------------------------- 148 * Definitions for initial stack pointer and data area 149 */ 150#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MONITOR_LEN 151#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ 152#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 153#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 154 155/* 156 * Low Level Configuration Settings 157 * (address mappings, register initial values, etc.) 158 * You should know what you are doing if you make changes here. 159 * For the detail description refer to the MPC8240 user's manual. 160 */ 161 162#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ 163#define CONFIG_SYS_HZ 1000 164 165#define CONFIG_SYS_ETH_DEV_FN 0x7800 166#define CONFIG_SYS_ETH_IOBASE 0x00104000 167 168 /* Bit-field values for MCCR1. 169 */ 170#define CONFIG_SYS_ROMNAL 0xf 171#define CONFIG_SYS_ROMFAL 0x1f 172#define CONFIG_SYS_DBUS_SIZE 0x3 173 174 /* Bit-field values for MCCR2. 175 */ 176#define CONFIG_SYS_TSWAIT 0x5 /* Transaction Start Wait States timer */ 177#define CONFIG_SYS_REFINT 0x400 /* Refresh interval FIXME: was 0t430 */ 178 179 /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. 180 */ 181#define CONFIG_SYS_BSTOPRE 0 /* FIXME: was 192 */ 182 183 /* Bit-field values for MCCR3. 184 */ 185#define CONFIG_SYS_REFREC 2 /* Refresh to activate interval */ 186 187 /* Bit-field values for MCCR4. 188 */ 189#define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval FIXME: was 2 */ 190#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval FIXME: was 5 */ 191#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */ 192#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */ 193#define CONFIG_SYS_SDMODE_BURSTLEN 3 /* SDMODE Burst length */ 194#define CONFIG_SYS_ACTORW 0xa /* FIXME was 2 */ 195#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 196 197#define CONFIG_SYS_PGMAX 0x0 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/ 198 199#define CONFIG_SYS_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */ 200 201/* Memory bank settings. 202 * Only bits 20-29 are actually used from these vales to set the 203 * start/end addresses. The upper two bits will always be 0, and the lower 204 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end 205 * address. Refer to the MPC8240 book. 206 */ 207 208#define CONFIG_SYS_BANK0_START 0x00000000 209#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) 210#define CONFIG_SYS_BANK0_ENABLE 1 211#define CONFIG_SYS_BANK1_START 0x3ff00000 212#define CONFIG_SYS_BANK1_END 0x3fffffff 213#define CONFIG_SYS_BANK1_ENABLE 0 214#define CONFIG_SYS_BANK2_START 0x3ff00000 215#define CONFIG_SYS_BANK2_END 0x3fffffff 216#define CONFIG_SYS_BANK2_ENABLE 0 217#define CONFIG_SYS_BANK3_START 0x3ff00000 218#define CONFIG_SYS_BANK3_END 0x3fffffff 219#define CONFIG_SYS_BANK3_ENABLE 0 220#define CONFIG_SYS_BANK4_START 0x3ff00000 221#define CONFIG_SYS_BANK4_END 0x3fffffff 222#define CONFIG_SYS_BANK4_ENABLE 0 223#define CONFIG_SYS_BANK5_START 0x3ff00000 224#define CONFIG_SYS_BANK5_END 0x3fffffff 225#define CONFIG_SYS_BANK5_ENABLE 0 226#define CONFIG_SYS_BANK6_START 0x3ff00000 227#define CONFIG_SYS_BANK6_END 0x3fffffff 228#define CONFIG_SYS_BANK6_ENABLE 0 229#define CONFIG_SYS_BANK7_START 0x3ff00000 230#define CONFIG_SYS_BANK7_END 0x3fffffff 231#define CONFIG_SYS_BANK7_ENABLE 0 232 233#define CONFIG_SYS_ODCR 0xff 234 235#define CONFIG_PCI 1 /* Include PCI support */ 236#undef CONFIG_PCI_PNP 237 238/* PCI Memory space(s) */ 239#define PCI_MEM_SPACE1_START 0x80000000 240#define PCI_MEM_SPACE2_START 0xfd000000 241 242/* ROM Spaces */ 243#include "../board/bmw/bmw.h" 244 245/* BAT configuration */ 246#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 247#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 248 249#define CONFIG_SYS_IBAT1L (0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT) 250#define CONFIG_SYS_IBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP) 251 252#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) 253#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) 254 255#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) 256#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 257 258#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 259#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 260#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 261#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 262#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 263#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 264#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 265#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 266 267/* 268 * For booting Linux, the board info and command line data 269 * have to be in the first 8 MB of memory, since this is 270 * the maximum mapped by the Linux kernel during initialization. 271 */ 272#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 273 274/* 275 * FLASH organization 276 */ 277#define CONFIG_SYS_MAX_FLASH_BANKS 0 /* Max number of flash banks */ 278#define CONFIG_SYS_MAX_FLASH_SECT 64 /* Max number of sectors per flash */ 279 280#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 281#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 282 283/* 284 * Warining: environment is not EMBEDDED in the U-Boot code. 285 * It's stored in flash separately. 286 */ 287#define CONFIG_ENV_IS_IN_NVRAM 1 288#define CONFIG_ENV_OVERWRITE 1 289#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE 1 290#define CONFIG_ENV_ADDR 0x7c004000 /* right at the start of NVRAM */ 291#define CONFIG_ENV_SIZE 0x1ff0 /* Size of the Environment - 8K */ 292#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */ 293 294/* 295 * Cache Configuration 296 */ 297#define CONFIG_SYS_CACHELINE_SIZE 32 298#if defined(CONFIG_CMD_KGDB) 299# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 300#endif 301 302#endif /* __CONFIG_H */ 303