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28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31
32
33
34
35
36#define CONFIG_405GP 1
37#define CONFIG_4xx 1
38#define CONFIG_CPCI405 1
39#define CONFIG_CPCI405_VER2 1
40#undef CONFIG_CPCI405_6U
41
42#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
43
44#define CONFIG_BOARD_EARLY_INIT_F 1
45#define CONFIG_MISC_INIT_R 1
46
47#define CONFIG_SYS_CLK_FREQ 33330000
48
49#define CONFIG_BAUDRATE 9600
50#define CONFIG_BOOTDELAY 3
51
52#undef CONFIG_BOOTARGS
53#undef CONFIG_BOOTCOMMAND
54
55#define CONFIG_PREBOOT
56
57#define CONFIG_LOADS_ECHO 1
58#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
59
60#define CONFIG_PPC4xx_EMAC
61#define CONFIG_MII 1
62#define CONFIG_PHY_ADDR 0
63#define CONFIG_LXT971_NO_SLEEP 1
64#define CONFIG_RESET_PHY_R 1
65
66#undef CONFIG_HAS_ETH1
67
68#define CONFIG_RTC_M48T35A 1
69
70
71
72
73#define CONFIG_BOOTP_SUBNETMASK
74#define CONFIG_BOOTP_GATEWAY
75#define CONFIG_BOOTP_HOSTNAME
76#define CONFIG_BOOTP_BOOTPATH
77#define CONFIG_BOOTP_DNS
78#define CONFIG_BOOTP_DNS2
79#define CONFIG_BOOTP_SEND_HOSTNAME
80
81
82
83
84
85#include <config_cmd_default.h>
86
87#define CONFIG_CMD_DHCP
88#define CONFIG_CMD_PCI
89#define CONFIG_CMD_IRQ
90#define CONFIG_CMD_IDE
91#define CONFIG_CMD_FAT
92#define CONFIG_CMD_ELF
93#define CONFIG_CMD_DATE
94#define CONFIG_CMD_I2C
95#define CONFIG_CMD_MII
96#define CONFIG_CMD_PING
97#define CONFIG_CMD_BSP
98#define CONFIG_CMD_EEPROM
99
100#define CONFIG_MAC_PARTITION
101#define CONFIG_DOS_PARTITION
102
103#define CONFIG_SUPPORT_VFAT
104
105#undef CONFIG_WATCHDOG
106
107#define CONFIG_SDRAM_BANK0 1
108
109
110
111
112#define CONFIG_SYS_LONGHELP
113#define CONFIG_SYS_PROMPT "=> "
114
115#undef CONFIG_SYS_HUSH_PARSER
116
117#if defined(CONFIG_CMD_KGDB)
118#define CONFIG_SYS_CBSIZE 1024
119#else
120#define CONFIG_SYS_CBSIZE 256
121#endif
122#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
123#define CONFIG_SYS_MAXARGS 16
124#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
125
126#define CONFIG_SYS_DEVICE_NULLDEV 1
127
128#define CONFIG_SYS_CONSOLE_INFO_QUIET 1
129
130#define CONFIG_AUTO_COMPLETE 1
131
132#define CONFIG_SYS_MEMTEST_START 0x0400000
133#define CONFIG_SYS_MEMTEST_END 0x0C00000
134
135#define CONFIG_CONS_INDEX 1
136#define CONFIG_SYS_NS16550
137#define CONFIG_SYS_NS16550_SERIAL
138#define CONFIG_SYS_NS16550_REG_SIZE 1
139#define CONFIG_SYS_NS16550_CLK get_serial_clock()
140
141#undef CONFIG_SYS_EXT_SERIAL_CLOCK
142#define CONFIG_SYS_BASE_BAUD 691200
143
144
145#define CONFIG_SYS_BAUDRATE_TABLE \
146 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
147 57600, 115200, 230400, 460800, 921600 }
148
149#define CONFIG_SYS_LOAD_ADDR 0x100000
150#define CONFIG_SYS_EXTBDINFO 1
151
152#define CONFIG_SYS_HZ 1000
153
154#define CONFIG_CMDLINE_EDITING
155
156#define CONFIG_LOOPW 1
157
158#define CONFIG_ZERO_BOOTDELAY_CHECK
159
160#define CONFIG_VERSION_VARIABLE 1
161
162#define CONFIG_AUTOBOOT_KEYED 1
163#define CONFIG_AUTOBOOT_PROMPT \
164 "Press SPACE to abort autoboot in %d seconds\n", bootdelay
165#undef CONFIG_AUTOBOOT_DELAY_STR
166#define CONFIG_AUTOBOOT_STOP_STR " "
167
168#define CONFIG_SYS_RX_ETH_BUFFER 16
169
170
171
172
173
174#define PCI_HOST_ADAPTER 0
175#define PCI_HOST_FORCE 1
176#define PCI_HOST_AUTO 2
177
178#define CONFIG_PCI
179#define CONFIG_PCI_HOST PCI_HOST_AUTO
180#define CONFIG_PCI_PNP
181
182
183#define CONFIG_PCI_SCAN_SHOW
184
185#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1
186
187#define CONFIG_PCI_BOOTDELAY 0
188
189#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE
190#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405
191#define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406
192#define CONFIG_SYS_PCI_CLASSCODE 0x0b20
193#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart)
194#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1)
195#define CONFIG_SYS_PCI_PTM1PCI 0x00000000
196#define CONFIG_SYS_PCI_PTM2LA 0xffc00000
197#define CONFIG_SYS_PCI_PTM2MS 0xffc00001
198#define CONFIG_SYS_PCI_PTM2PCI 0x04000000
199
200#define CONFIG_PCI_4xx_PTM_OVERWRITE 1
201
202
203
204
205
206#undef CONFIG_IDE_8xx_DIRECT
207#undef CONFIG_IDE_LED
208#define CONFIG_IDE_RESET 1
209
210#define CONFIG_SYS_IDE_MAXBUS 1
211#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1)
212
213#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
214#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
215
216#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000
217#define CONFIG_SYS_ATA_REG_OFFSET 0x0000
218#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000
219
220
221
222
223
224
225#define CONFIG_SYS_SDRAM_BASE 0x00000000
226#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
227#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
228#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
229#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
230
231#define CONFIG_PRAM 0
232
233
234
235
236
237
238#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
239
240#define CONFIG_OF_LIBFDT
241#define CONFIG_OF_BOARD_SETUP
242
243
244
245
246#define CONFIG_SYS_MAX_FLASH_BANKS 2
247#define CONFIG_SYS_MAX_FLASH_SECT 256
248
249#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
250#define CONFIG_SYS_FLASH_WRITE_TOUT 500
251
252#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short
253#define CONFIG_SYS_FLASH_ADDR0 0x5555
254#define CONFIG_SYS_FLASH_ADDR1 0x2AAA
255
256
257
258
259#define CONFIG_SYS_FLASH_READ0 0x0000
260#define CONFIG_SYS_FLASH_READ1 0x0001
261#define CONFIG_SYS_FLASH_READ2 0x0002
262
263#define CONFIG_SYS_FLASH_EMPTY_INFO
264
265#if 0
266
267
268
269#define CONFIG_ENV_IS_IN_NVRAM 1
270#define CONFIG_ENV_SIZE 0x0ff8
271#define CONFIG_ENV_ADDR \
272 (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-(CONFIG_ENV_SIZE+8))
273
274#else
275
276#define CONFIG_ENV_IS_IN_EEPROM 1
277#define CONFIG_ENV_OFFSET 0x000
278#define CONFIG_ENV_SIZE 0x800
279
280#endif
281
282#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000
283#define CONFIG_SYS_NVRAM_SIZE (32*1024)
284#define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900)
285
286
287
288
289#define CONFIG_HARD_I2C
290#define CONFIG_PPC4XX_I2C
291#define CONFIG_SYS_I2C_SPEED 400000
292#define CONFIG_SYS_I2C_SLAVE 0x7F
293
294#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
295#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
296
297#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
298#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
299
300
301#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
302
303
304
305
306
307
308
309#define FLASH_BASE0_PRELIM 0xFF800000
310#define FLASH_BASE1_PRELIM 0xFFC00000
311
312
313
314
315
316
317#define CONFIG_SYS_EBC_PB0AP 0x92015480
318#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000
319
320
321#define CONFIG_SYS_EBC_PB1AP 0x92015480
322#define CONFIG_SYS_EBC_PB1CR 0xFF85A000
323
324
325#define CONFIG_SYS_EBC_PB2AP 0x010053C0
326#define CONFIG_SYS_EBC_PB2CR 0xF0018000
327#define CONFIG_SYS_LED_ADDR 0xF0000380
328
329
330#define CONFIG_SYS_EBC_PB3AP 0x010053C0
331#define CONFIG_SYS_EBC_PB3CR 0xF011A000
332
333
334
335#define CONFIG_SYS_EBC_PB4AP 0x01805680
336#define CONFIG_SYS_EBC_PB4CR 0xF0218000
337
338
339#define CONFIG_SYS_EBC_PB5AP 0x04005B80
340#define CONFIG_SYS_EBC_PB5CR 0xF0318000
341
342
343#define CONFIG_SYS_EBC_PB6AP 0x010053C0
344#define CONFIG_SYS_EBC_PB6CR 0xF041A000
345#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0400000
346
347
348
349
350
351#define CONFIG_SYS_FPGA_MODE 0x00
352#define CONFIG_SYS_FPGA_STATUS 0x02
353#define CONFIG_SYS_FPGA_TS 0x04
354#define CONFIG_SYS_FPGA_TS_LOW 0x06
355#define CONFIG_SYS_FPGA_TS_CAP0 0x10
356#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12
357#define CONFIG_SYS_FPGA_TS_CAP1 0x14
358#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16
359#define CONFIG_SYS_FPGA_TS_CAP2 0x18
360#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a
361#define CONFIG_SYS_FPGA_TS_CAP3 0x1c
362#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e
363
364
365#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001
366#define CONFIG_SYS_FPGA_MODE_DUART_RESET 0x0002
367#define CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT 0x0004
368#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
369#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000
370#define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000
371
372
373#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001
374#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002
375#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004
376#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008
377#define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000
378
379#define CONFIG_SYS_FPGA_SPARTAN2 1
380#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024
381
382
383#define CONFIG_SYS_FPGA_PRG 0x04000000
384#define CONFIG_SYS_FPGA_CLK 0x02000000
385#define CONFIG_SYS_FPGA_DATA 0x01000000
386#define CONFIG_SYS_FPGA_INIT 0x00010000
387#define CONFIG_SYS_FPGA_DONE 0x00008000
388
389
390
391
392#define CONFIG_SYS_INIT_DCACHE_CS 7
393
394#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
395#define CONFIG_SYS_INIT_RAM_SIZE 0x2000
396#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
397#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
398
399#endif
400