1/* 2 * (C) Copyright 2001-2003 3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* 25 * board/config.h - configuration options, board specific 26 */ 27 28#ifndef __CONFIG_H 29#define __CONFIG_H 30 31/* 32 * High Level Configuration Options 33 * (easy to change) 34 */ 35 36#define CONFIG_405GP 1 /* This is a PPC405 CPU */ 37#define CONFIG_4xx 1 /* ...member of PPC4xx family */ 38#define CONFIG_CPCIISER4 1 /* ...on a CPCIISER4 board */ 39 40#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 41 42#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ 43 44#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ 45 46#define CONFIG_BAUDRATE 9600 47#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ 48 49#undef CONFIG_BOOTARGS 50#define CONFIG_BOOTCOMMAND "bootm fff00000" 51 52#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 53#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 54 55#define CONFIG_PPC4xx_EMAC 56#define CONFIG_MII 1 /* MII PHY management */ 57#define CONFIG_PHY_ADDR 0 /* PHY address */ 58#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ 59 60 61/* 62 * BOOTP options 63 */ 64#define CONFIG_BOOTP_BOOTFILESIZE 65#define CONFIG_BOOTP_BOOTPATH 66#define CONFIG_BOOTP_GATEWAY 67#define CONFIG_BOOTP_HOSTNAME 68 69 70/* 71 * BOOTP options 72 */ 73#define CONFIG_BOOTP_BOOTFILESIZE 74#define CONFIG_BOOTP_BOOTPATH 75#define CONFIG_BOOTP_GATEWAY 76#define CONFIG_BOOTP_HOSTNAME 77 78 79/* 80 * Command line configuration. 81 */ 82#include <config_cmd_default.h> 83 84#define CONFIG_CMD_PCI 85#define CONFIG_CMD_IRQ 86#define CONFIG_CMD_MII 87#define CONFIG_CMD_ELF 88#define CONFIG_CMD_EEPROM 89 90 91#undef CONFIG_WATCHDOG /* watchdog disabled */ 92 93#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ 94 95/* 96 * Miscellaneous configurable options 97 */ 98#define CONFIG_SYS_LONGHELP /* undef to save memory */ 99#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 100#if defined(CONFIG_CMD_KGDB) 101#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 102#else 103#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 104#endif 105#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 106#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 107#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 108 109#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ 110 111#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 112#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 113 114#define CONFIG_CONS_INDEX 1 /* Use UART0 */ 115#define CONFIG_SYS_NS16550 116#define CONFIG_SYS_NS16550_SERIAL 117#define CONFIG_SYS_NS16550_REG_SIZE 1 118#define CONFIG_SYS_NS16550_CLK get_serial_clock() 119 120#define CONFIG_SYS_EXT_SERIAL_CLOCK 1843200 /* use external serial clock */ 121 122/* The following table includes the supported baudrates */ 123#define CONFIG_SYS_BAUDRATE_TABLE \ 124 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ 125 57600, 115200, 230400, 460800, 921600 } 126 127#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 128#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ 129 130#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 131 132#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ 133 134/*----------------------------------------------------------------------- 135 * PCI stuff 136 *----------------------------------------------------------------------- 137 */ 138#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ 139#define PCI_HOST_FORCE 1 /* configure as pci host */ 140#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ 141 142#define CONFIG_PCI /* include pci support */ 143#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ 144#define CONFIG_PCI_PNP /* do pci plug-and-play */ 145 /* resource configuration */ 146 147#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ 148#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0404 /* PCI Device ID: CPCI-ISER4 */ 149#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ 150#define CONFIG_SYS_PCI_PTM1MS 0xff000001 /* 16MB, enable hard-wired to 1 */ 151#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ 152#define CONFIG_SYS_PCI_PTM2LA 0xffe00000 /* point to flash */ 153#define CONFIG_SYS_PCI_PTM2MS 0xffe00001 /* 2MB, enable */ 154#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ 155 156/*----------------------------------------------------------------------- 157 * Start addresses for the final memory configuration 158 * (Set up by the startup code) 159 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 160 */ 161#define CONFIG_SYS_SDRAM_BASE 0x00000000 162#define CONFIG_SYS_FLASH_BASE 0xFFFC0000 163#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 164#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ 165#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ 166 167/* 168 * For booting Linux, the board info and command line data 169 * have to be in the first 8 MB of memory, since this is 170 * the maximum mapped by the Linux kernel during initialization. 171 */ 172#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 173/*----------------------------------------------------------------------- 174 * FLASH organization 175 */ 176#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 177#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 178 179#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 180#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 181 182#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ 183#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ 184#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ 185/* 186 * The following defines are added for buggy IOP480 byte interface. 187 * All other boards should use the standard values (CPCI405 etc.) 188 */ 189#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ 190#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ 191#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ 192 193#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ 194 195/*----------------------------------------------------------------------- 196 * I2C EEPROM (CAT24WC08) for environment 197 */ 198#define CONFIG_HARD_I2C /* I2C with hardware support */ 199#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ 200#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 201#define CONFIG_SYS_I2C_SLAVE 0x7F 202 203#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ 204#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ 205/* mask of address bits that overflow into the "EEPROM chip address" */ 206#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 207#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ 208 /* 16 byte page write mode using*/ 209 /* last 4 bits of the address */ 210#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ 211 212#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ 213#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ 214#define CONFIG_ENV_SIZE 0x300 /* 768 bytes may be used for env vars */ 215 /* total size of a CAT24WC08 is 1024 bytes */ 216 217/* 218 * Init Memory Controller: 219 * 220 * BR0/1 and OR0/1 (FLASH) 221 */ 222 223#define FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank #0 */ 224#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ 225 226/*----------------------------------------------------------------------- 227 * External Bus Controller (EBC) Setup 228 */ 229 230/* Memory Bank 0 (Flash Bank 0) initialization */ 231#define CONFIG_SYS_EBC_PB0AP 0x92015480 232#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ 233 234/* Memory Bank 1 (Uart 8bit) initialization */ 235#define CONFIG_SYS_EBC_PB1AP 0x01000480 /* TWT=2,TH=2,no Ready,BEM=0,SOR=1 */ 236#define CONFIG_SYS_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ 237 238/* Memory Bank 2 (Uart 32bit) initialization */ 239#define CONFIG_SYS_EBC_PB2AP 0x000004c0 /* no Ready, BEM=1 */ 240#define CONFIG_SYS_EBC_PB2CR 0xF011C000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */ 241 242/* Memory Bank 3 (FPGA Reset) initialization */ 243#define CONFIG_SYS_EBC_PB3AP 0x010004C0 /* no Ready, BEM=1 */ 244#define CONFIG_SYS_EBC_PB3CR 0xF021A000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=16bit */ 245 246/*----------------------------------------------------------------------- 247 * Definitions for initial stack pointer and data area (in DPRAM) 248 */ 249#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */ 250#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */ 251#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */ 252#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 253#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 254 255#endif /* __CONFIG_H */ 256