1/* 2 * (C) Copyright 2000 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * Keith Outwater, keith_outwater@mvis.com 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25/* 26 * board/config_GEN860T.h - board specific configuration options 27 */ 28 29#ifndef __CONFIG_GEN860T_H 30#define __CONFIG_H 31 32/* 33 * High Level Configuration Options 34 */ 35#define CONFIG_MPC860 36#define CONFIG_GEN860T 37 38#define CONFIG_SYS_TEXT_BASE 0x40000000 39 40/* 41 * Identify the board 42 */ 43#if !defined(CONFIG_SC) 44#define CONFIG_IDENT_STRING " B2" 45#else 46#define CONFIG_IDENT_STRING " SC" 47#endif 48 49/* 50 * Don't depend on the RTC clock to determine clock frequency - 51 * the 860's internal rtc uses a 32.768 KHz clock which is 52 * generated by the DS1337 - and the DS1337 clock can be turned off. 53 */ 54#if !defined(CONFIG_SC) 55#define CONFIG_8xx_GCLK_FREQ 66600000 56#else 57#define CONFIG_8xx_GCLK_FREQ 48000000 58#endif 59 60/* 61 * The RS-232 console port is on SMC1 62 */ 63#define CONFIG_8xx_CONS_SMC1 64#define CONFIG_BAUDRATE 38400 65 66/* 67 * Print console information 68 */ 69#undef CONFIG_SYS_CONSOLE_INFO_QUIET 70 71/* 72 * Set the autoboot delay in seconds. A delay of -1 disables autoboot 73 */ 74#define CONFIG_BOOTDELAY 5 75 76/* 77 * Pass the clock frequency to the Linux kernel in units of MHz 78 */ 79#define CONFIG_CLOCKS_IN_MHZ 80 81#define CONFIG_PREBOOT \ 82 "echo;echo" 83 84#undef CONFIG_BOOTARGS 85#define CONFIG_BOOTCOMMAND \ 86 "bootp;" \ 87 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ 88 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ 89 "bootm" 90 91/* 92 * Turn off echo for serial download by default. Allow baud rate to be changed 93 * for downloads 94 */ 95#undef CONFIG_LOADS_ECHO 96#define CONFIG_SYS_LOADS_BAUD_CHANGE 97 98/* 99 * Set default load address for tftp network downloads 100 */ 101#define CONFIG_SYS_TFTP_LOADADDR 0x01000000 102 103/* 104 * Turn off the watchdog timer 105 */ 106#undef CONFIG_WATCHDOG 107 108/* 109 * Do not reboot if a panic occurs 110 */ 111#define CONFIG_PANIC_HANG 112 113/* 114 * Enable the status LED 115 */ 116#define CONFIG_STATUS_LED 117 118/* 119 * Reset address. We pick an address such that when an instruction 120 * is executed at that address, a machine check exception occurs 121 */ 122#define CONFIG_SYS_RESET_ADDRESS ((ulong) -1) 123 124/* 125 * BOOTP options 126 */ 127#define CONFIG_BOOTP_SUBNETMASK 128#define CONFIG_BOOTP_GATEWAY 129#define CONFIG_BOOTP_HOSTNAME 130#define CONFIG_BOOTP_BOOTPATH 131#define CONFIG_BOOTP_BOOTFILESIZE 132 133 134/* 135 * The GEN860T network interface uses the on-chip 10/100 FEC with 136 * an Intel LXT971A PHY connected to the 860T's MII. The PHY's 137 * MII address is hardwired on the board to zero. 138 */ 139#define CONFIG_FEC_ENET 140#define CONFIG_SYS_DISCOVER_PHY 141#define CONFIG_MII 142#define CONFIG_MII_INIT 1 143#define CONFIG_PHY_ADDR 0 144 145/* 146 * Set default IP stuff just to get bootstrap entries into the 147 * environment so that we can source the full default environment. 148 */ 149#define CONFIG_ETHADDR 9a:52:63:15:85:25 150#define CONFIG_SERVERIP 10.0.4.201 151#define CONFIG_IPADDR 10.0.4.111 152 153/* 154 * This board has a 32 kibibyte EEPROM (Atmel AT24C256) connected to 155 * the MPC860T I2C interface. 156 */ 157#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 158#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ 159#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10 mS w/ 20% margin */ 160#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* need 16 bit address */ 161#define CONFIG_ENV_EEPROM_SIZE (32 * 1024) 162 163/* 164 * Enable I2C and select the hardware/software driver 165 */ 166#define CONFIG_HARD_I2C 1 /* CPM based I2C */ 167#undef CONFIG_SOFT_I2C /* Bit-banged I2C */ 168 169#ifdef CONFIG_HARD_I2C 170#define CONFIG_SYS_I2C_SPEED 100000 /* clock speed in Hz */ 171#define CONFIG_SYS_I2C_SLAVE 0xFE /* I2C slave address */ 172#endif 173 174#ifdef CONFIG_SOFT_I2C 175#define PB_SCL 0x00000020 /* PB 26 */ 176#define PB_SDA 0x00000010 /* PB 27 */ 177#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) 178#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) 179#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) 180#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) 181#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ 182 else immr->im_cpm.cp_pbdat &= ~PB_SDA 183#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ 184 else immr->im_cpm.cp_pbdat &= ~PB_SCL 185#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ 186#endif 187 188/* 189 * Allow environment overwrites by anyone 190 */ 191#define CONFIG_ENV_OVERWRITE 192 193#if !defined(CONFIG_SC) 194/* 195 * The MPC860's internal RTC is horribly broken in rev D masks. Three 196 * internal MPC860T circuit nodes were inadvertently left floating; this 197 * causes KAPWR current in power down mode to be three orders of magnitude 198 * higher than specified in the datasheet (from 10 uA to 10 mA). No 199 * reasonable battery can keep that kind RTC running during powerdown for any 200 * length of time, so we use an external RTC on the I2C bus instead. 201 */ 202#define CONFIG_RTC_DS1337 203#define CONFIG_SYS_I2C_RTC_ADDR 0x68 204 205#else 206/* 207 * No external RTC on SC variant, so we're stuck with the internal one. 208 */ 209#define CONFIG_RTC_MPC8xx 210#endif 211 212/* 213 * Power On Self Test support 214 */ 215#define CONFIG_POST ( CONFIG_SYS_POST_CACHE | \ 216 CONFIG_SYS_POST_MEMORY | \ 217 CONFIG_SYS_POST_CPU | \ 218 CONFIG_SYS_POST_UART | \ 219 CONFIG_SYS_POST_SPR ) 220 221 222/* 223 * Command line configuration. 224 */ 225#include <config_cmd_default.h> 226 227#define CONFIG_CMD_ASKENV 228#define CONFIG_CMD_DHCP 229#define CONFIG_CMD_I2C 230#define CONFIG_CMD_EEPROM 231#define CONFIG_CMD_REGINFO 232#define CONFIG_CMD_IMMAP 233#define CONFIG_CMD_ELF 234#define CONFIG_CMD_DATE 235#define CONFIG_CMD_FPGA 236#define CONFIG_CMD_MII 237#define CONFIG_CMD_BEDBUG 238 239#ifdef CONFIG_POST 240#define CONFIG_CMD_DIAG 241#endif 242 243/* 244 * There is no IDE/PCMCIA hardware support on the board. 245 */ 246#undef CONFIG_IDE_PCMCIA 247#undef CONFIG_IDE_LED 248#undef CONFIG_IDE_RESET 249 250/* 251 * Enable the call to misc_init_r() for miscellaneous platform 252 * dependent initialization. 253 */ 254#define CONFIG_MISC_INIT_R 255 256/* 257 * Enable call to last_stage_init() so we can twiddle some LEDS :) 258 */ 259#define CONFIG_LAST_STAGE_INIT 260 261/* 262 * Virtex2 FPGA configuration support 263 */ 264#define CONFIG_FPGA_COUNT 1 265#define CONFIG_FPGA 266#define CONFIG_FPGA_XILINX 267#define CONFIG_FPGA_VIRTEX2 268#define CONFIG_SYS_FPGA_PROG_FEEDBACK 269 270/* 271 * Verbose help from command monitor. 272 */ 273#define CONFIG_SYS_LONGHELP 274#if !defined(CONFIG_SC) 275#define CONFIG_SYS_PROMPT "B2> " 276#else 277#define CONFIG_SYS_PROMPT "SC> " 278#endif 279 280 281/* 282 * Use the "hush" command parser 283 */ 284#define CONFIG_SYS_HUSH_PARSER 285 286/* 287 * Set buffer size for console I/O 288 */ 289#if defined(CONFIG_CMD_KGDB) 290#define CONFIG_SYS_CBSIZE 1024 291#else 292#define CONFIG_SYS_CBSIZE 256 293#endif 294 295/* 296 * Print buffer size 297 */ 298#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 299 300/* 301 * Maximum number of arguments that a command can accept 302 */ 303#define CONFIG_SYS_MAXARGS 16 304 305/* 306 * Boot argument buffer size 307 */ 308#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 309 310/* 311 * Default memory test range 312 */ 313#define CONFIG_SYS_MEMTEST_START 0x0100000 314#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (128 * 1024)) 315 316/* 317 * Select the more full-featured memory test 318 */ 319#define CONFIG_SYS_ALT_MEMTEST 320 321/* 322 * Default load address 323 */ 324#define CONFIG_SYS_LOAD_ADDR 0x01000000 325 326/* 327 * Set decrementer frequency (1 ms ticks) 328 */ 329#define CONFIG_SYS_HZ 1000 330 331/* 332 * Device memory map (after SDRAM remap to 0x0): 333 * 334 * CS Device Base Addr Size 335 * ---------------------------------------------------- 336 * CS0* Flash 0x40000000 64 M 337 * CS1* SDRAM 0x00000000 16 M 338 * CS2* Disk-On-Chip 0x50000000 32 K 339 * CS3* FPGA 0x60000000 64 M 340 * CS4* SelectMap 0x70000000 32 K 341 * CS5* Mil-Std 1553 I/F 0x80000000 32 K 342 * CS6* Unused 343 * CS7* Unused 344 * IMMR 860T Registers 0xfff00000 345 */ 346 347/* 348 * Base addresses and block sizes 349 */ 350#define CONFIG_SYS_IMMR 0xFF000000 351 352#define SDRAM_BASE 0x00000000 353#define SDRAM_SIZE (64 * 1024 * 1024) 354 355#define FLASH_BASE 0x40000000 356#define FLASH_SIZE (16 * 1024 * 1024) 357 358#define DOC_BASE 0x50000000 359#define DOC_SIZE (32 * 1024) 360 361#define FPGA_BASE 0x60000000 362#define FPGA_SIZE (64 * 1024 * 1024) 363 364#define SELECTMAP_BASE 0x70000000 365#define SELECTMAP_SIZE (32 * 1024) 366 367#define M1553_BASE 0x80000000 368#define M1553_SIZE (64 * 1024) 369 370/* 371 * Definitions for initial stack pointer and data area (in DPRAM) 372 */ 373#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 374#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ 375#define CONFIG_SYS_INIT_DATA_SIZE 64 /* # bytes reserved for initial data*/ 376#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_DATA_SIZE) 377#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 378 379/* 380 * Start addresses for the final memory configuration 381 * (Set up by the startup code) 382 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 383 */ 384#define CONFIG_SYS_SDRAM_BASE SDRAM_BASE 385 386/* 387 * FLASH organization 388 */ 389#define CONFIG_SYS_FLASH_BASE FLASH_BASE 390#define CONFIG_SYS_FLASH_SIZE FLASH_SIZE 391#define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024) 392#define CONFIG_SYS_MAX_FLASH_BANKS 1 393#define CONFIG_SYS_MAX_FLASH_SECT 128 394 395/* 396 * The timeout values are for an entire chip and are in milliseconds. 397 * Yes I know that the write timeout is huge. Accroding to the 398 * datasheet a single byte takes 630 uS (round to 1 ms) max at worst 399 * case VCC and temp after 100K programming cycles. It works out 400 * to 280 minutes (might as well be forever). 401 */ 402#define CONFIG_SYS_FLASH_ERASE_TOUT (CONFIG_SYS_MAX_FLASH_SECT * 5000) 403#define CONFIG_SYS_FLASH_WRITE_TOUT (CONFIG_SYS_MAX_FLASH_SECT * 128 * 1024 * 1) 404 405/* 406 * Allow direct writes to FLASH from tftp transfers (** dangerous **) 407 */ 408#define CONFIG_SYS_DIRECT_FLASH_TFTP 409 410/* 411 * Reserve memory for U-Boot. 412 */ 413#define CONFIG_SYS_MAX_UBOOT_SECTS 4 414#define CONFIG_SYS_MONITOR_LEN (CONFIG_SYS_MAX_UBOOT_SECTS * CONFIG_SYS_FLASH_SECT_SIZE) 415#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 416 417/* 418 * Select environment placement. NOTE that u-boot.lds must 419 * be edited if this is changed! 420 */ 421#undef CONFIG_ENV_IS_IN_FLASH 422#define CONFIG_ENV_IS_IN_EEPROM 423 424#if defined(CONFIG_ENV_IS_IN_EEPROM) 425#define CONFIG_ENV_SIZE (2 * 1024) 426#define CONFIG_ENV_OFFSET (CONFIG_ENV_EEPROM_SIZE - (8 * 1024)) 427#else 428#define CONFIG_ENV_SIZE 0x1000 429#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SIZE 430 431/* 432 * This ultimately gets passed right into the linker script, so we have to 433 * use a number :( 434 */ 435#define CONFIG_ENV_OFFSET 0x060000 436#endif 437 438/* 439 * Reserve memory for malloc() 440 */ 441#define CONFIG_SYS_MALLOC_LEN (128 * 1024) 442 443/* 444 * For booting Linux, the board info and command line data 445 * have to be in the first 8 MB of memory, since this is 446 * the maximum mapped by the Linux kernel during initialization. 447 */ 448#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 449 450/* 451 * Cache Configuration 452 */ 453#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 454#if defined(CONFIG_CMD_KGDB) 455#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of above value */ 456#endif 457 458/*------------------------------------------------------------------------ 459 * SYPCR - System Protection Control UM 11-9 460 * ----------------------------------------------------------------------- 461 * SYPCR can only be written once after reset! 462 * 463 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 464 */ 465#if defined(CONFIG_WATCHDOG) 466#define CONFIG_SYS_SYPCR ( SYPCR_SWTC | \ 467 SYPCR_BMT | \ 468 SYPCR_BME | \ 469 SYPCR_SWF | \ 470 SYPCR_SWE | \ 471 SYPCR_SWRI | \ 472 SYPCR_SWP \ 473 ) 474#else 475#define CONFIG_SYS_SYPCR ( SYPCR_SWTC | \ 476 SYPCR_BMT | \ 477 SYPCR_BME | \ 478 SYPCR_SWF | \ 479 SYPCR_SWP \ 480 ) 481#endif 482 483/*----------------------------------------------------------------------- 484 * SIUMCR - SIU Module Configuration UM 11-6 485 *----------------------------------------------------------------------- 486 * Set debug pin mux, enable SPKROUT and GPLB5*. 487 */ 488#define CONFIG_SYS_SIUMCR ( SIUMCR_DBGC11 | \ 489 SIUMCR_DBPC11 | \ 490 SIUMCR_MLRC11 | \ 491 SIUMCR_GB5E \ 492 ) 493 494/*----------------------------------------------------------------------- 495 * TBSCR - Time Base Status and Control UM 11-26 496 *----------------------------------------------------------------------- 497 * Clear Reference Interrupt Status, Timebase freeze enabled 498 */ 499#define CONFIG_SYS_TBSCR ( TBSCR_REFA | \ 500 TBSCR_REFB | \ 501 TBSCR_TBF \ 502 ) 503 504/*----------------------------------------------------------------------- 505 * RTCSC - Real-Time Clock Status and Control Register UM 11-27 506 *----------------------------------------------------------------------- 507 */ 508#define CONFIG_SYS_RTCSC ( RTCSC_SEC | \ 509 RTCSC_ALR | \ 510 RTCSC_RTF | \ 511 RTCSC_RTE \ 512 ) 513 514/*----------------------------------------------------------------------- 515 * PISCR - Periodic Interrupt Status and Control UM 11-31 516 *----------------------------------------------------------------------- 517 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 518 */ 519#define CONFIG_SYS_PISCR ( PISCR_PS | \ 520 PISCR_PITF \ 521 ) 522 523/*----------------------------------------------------------------------- 524 * PLPRCR - PLL, Low-Power, and Reset Control Register UM 15-30 525 *----------------------------------------------------------------------- 526 * Reset PLL lock status sticky bit, timer expired status bit and timer 527 * interrupt status bit. Set MF for 1:2:1 mode. 528 */ 529#define CONFIG_SYS_PLPRCR ( ((0x1 << PLPRCR_MF_SHIFT) & PLPRCR_MF_MSK) | \ 530 PLPRCR_SPLSS | \ 531 PLPRCR_TEXPS | \ 532 PLPRCR_TMIST \ 533 ) 534 535/*----------------------------------------------------------------------- 536 * SCCR - System Clock and reset Control Register UM 15-27 537 *----------------------------------------------------------------------- 538 * Set clock output, timebase and RTC source and divider, 539 * power management and some other internal clocks 540 */ 541#define SCCR_MASK SCCR_EBDF11 542 543#if !defined(CONFIG_SC) 544#define CONFIG_SYS_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \ 545 SCCR_COM00 | /* full strength CLKOUT */ \ 546 SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \ 547 SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \ 548 SCCR_DFNL000 | \ 549 SCCR_DFNH000 \ 550 ) 551#else 552#define CONFIG_SYS_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \ 553 SCCR_COM00 | /* full strength CLKOUT */ \ 554 SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \ 555 SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \ 556 SCCR_DFNL000 | \ 557 SCCR_DFNH000 | \ 558 SCCR_RTDIV | \ 559 SCCR_RTSEL \ 560 ) 561#endif 562 563/*----------------------------------------------------------------------- 564 * DER - Debug Enable Register UM 37-46 565 *----------------------------------------------------------------------- 566 * Mask all events that can cause entry into debug mode 567 */ 568#define CONFIG_SYS_DER 0 569 570/* 571 * Initialize Memory Controller: 572 * 573 * BR0 and OR0 (FLASH memory) 574 */ 575#define FLASH_BASE0_PRELIM FLASH_BASE 576 577/* 578 * Flash address mask 579 */ 580#define CONFIG_SYS_PRELIM_OR_AM 0xfe000000 581 582/* 583 * FLASH timing: 584 * 33 Mhz bus with ACS = 11, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 585 */ 586#define CONFIG_SYS_OR_TIMING_FLASH ( OR_CSNT_SAM | \ 587 OR_ACS_DIV2 | \ 588 OR_BI | \ 589 OR_SCY_2_CLK | \ 590 OR_TRLX | \ 591 OR_EHTR \ 592 ) 593 594#define CONFIG_SYS_OR0_PRELIM ( CONFIG_SYS_PRELIM_OR_AM | \ 595 CONFIG_SYS_OR_TIMING_FLASH \ 596 ) 597 598#define CONFIG_SYS_BR0_PRELIM ( (FLASH_BASE0_PRELIM & BR_BA_MSK) | \ 599 BR_MS_GPCM | \ 600 BR_PS_8 | \ 601 BR_V \ 602 ) 603 604/* 605 * SDRAM configuration 606 */ 607#define CONFIG_SYS_OR1_AM 0xfc000000 608#define CONFIG_SYS_OR1 ( (CONFIG_SYS_OR1_AM & OR_AM_MSK) | \ 609 OR_CSNT_SAM \ 610 ) 611 612#define CONFIG_SYS_BR1 ( (SDRAM_BASE & BR_BA_MSK) | \ 613 BR_MS_UPMA | \ 614 BR_PS_32 | \ 615 BR_V \ 616 ) 617 618/* 619 * Refresh rate 7.8 us (= 64 ms / 8K = 31.2 uS quad bursts) for one bank 620 * of 256 MBit SDRAM 621 */ 622#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 623 624/* 625 * Periodic timer for refresh @ 33 MHz system clock 626 */ 627#define CONFIG_SYS_MAMR_PTA 64 628 629/* 630 * MAMR settings for SDRAM 631 */ 632#define CONFIG_SYS_MAMR_8COL ( (CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | \ 633 MAMR_PTAE | \ 634 MAMR_AMA_TYPE_1 | \ 635 MAMR_DSA_1_CYCL | \ 636 MAMR_G0CLA_A10 | \ 637 MAMR_RLFA_1X | \ 638 MAMR_WLFA_1X | \ 639 MAMR_TLFA_4X \ 640 ) 641 642/* 643 * CS2* configuration for Disk On Chip: 644 * 33 MHz bus with TRLX=1, ACS=11, CSNT=1, EBDF=1, SCY=2, EHTR=1, 645 * no burst. 646 */ 647#define CONFIG_SYS_OR2_PRELIM ( (0xffff0000 & OR_AM_MSK) | \ 648 OR_CSNT_SAM | \ 649 OR_ACS_DIV2 | \ 650 OR_BI | \ 651 OR_SCY_2_CLK | \ 652 OR_TRLX | \ 653 OR_EHTR \ 654 ) 655 656#define CONFIG_SYS_BR2_PRELIM ( (DOC_BASE & BR_BA_MSK) | \ 657 BR_PS_8 | \ 658 BR_MS_GPCM | \ 659 BR_V \ 660 ) 661 662/* 663 * CS3* configuration for FPGA: 664 * 33 MHz bus with SCY=15, no burst. 665 * The FPGA uses TA and TEA to terminate bus cycles, but we 666 * clear SETA and set the cycle length to a large number so that 667 * the cycle will still complete even if there is a configuration 668 * error that prevents TA from asserting on FPGA accesss. 669 */ 670#define CONFIG_SYS_OR3_PRELIM ( (0xfc000000 & OR_AM_MSK) | \ 671 OR_SCY_15_CLK | \ 672 OR_BI \ 673 ) 674 675#define CONFIG_SYS_BR3_PRELIM ( (FPGA_BASE & BR_BA_MSK) | \ 676 BR_PS_32 | \ 677 BR_MS_GPCM | \ 678 BR_V \ 679 ) 680/* 681 * CS4* configuration for FPGA SelectMap configuration interface. 682 * 33 MHz bus, UPMB, no burst. Do not assert GPLB5 on falling edge 683 * of GCLK1_50 684 */ 685#define CONFIG_SYS_OR4_PRELIM ( (0xffff0000 & OR_AM_MSK) | \ 686 OR_G5LS | \ 687 OR_BI \ 688 ) 689 690#define CONFIG_SYS_BR4_PRELIM ( (SELECTMAP_BASE & BR_BA_MSK) | \ 691 BR_PS_8 | \ 692 BR_MS_UPMB | \ 693 BR_V \ 694 ) 695 696/* 697 * CS5* configuration for Mil-Std 1553 databus interface. 698 * 33 MHz bus, GPCM, no burst. 699 * The 1553 interface uses TA and TEA to terminate bus cycles, 700 * but we clear SETA and set the cycle length to a large number so that 701 * the cycle will still complete even if there is a configuration 702 * error that prevents TA from asserting on FPGA accesss. 703 */ 704#define CONFIG_SYS_OR5_PRELIM ( (0xffff0000 & OR_AM_MSK) | \ 705 OR_SCY_15_CLK | \ 706 OR_EHTR | \ 707 OR_TRLX | \ 708 OR_CSNT_SAM | \ 709 OR_BI \ 710 ) 711 712#define CONFIG_SYS_BR5_PRELIM ( (M1553_BASE & BR_BA_MSK) | \ 713 BR_PS_16 | \ 714 BR_MS_GPCM | \ 715 BR_V \ 716 ) 717 718/* 719 * FEC interrupt assignment 720 */ 721#define FEC_INTERRUPT SIU_LEVEL1 722 723/* 724 * Sanity checks 725 */ 726#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET) 727#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured 728#endif 729 730#endif /* __CONFIG_GEN860T_H */ 731