1/* 2 * Configuation settings for the Freescale MCF5485 FireEngine board. 3 * 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26/* 27 * board/config.h - configuration options, board specific 28 */ 29 30#ifndef _M5485EVB_H 31#define _M5485EVB_H 32 33/* 34 * High Level Configuration Options 35 * (easy to change) 36 */ 37#define CONFIG_MCF547x_8x /* define processor family */ 38#define CONFIG_M548x /* define processor type */ 39#define CONFIG_M5485 /* define processor type */ 40 41#define CONFIG_MCFUART 42#define CONFIG_SYS_UART_PORT (0) 43#define CONFIG_BAUDRATE 115200 44 45#define CONFIG_HW_WATCHDOG 46#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ 47 48/* Command line configuration */ 49#include <config_cmd_default.h> 50 51#define CONFIG_CMD_CACHE 52#undef CONFIG_CMD_DATE 53#define CONFIG_CMD_ELF 54#define CONFIG_CMD_FLASH 55#define CONFIG_CMD_I2C 56#define CONFIG_CMD_MEMORY 57#define CONFIG_CMD_MISC 58#define CONFIG_CMD_MII 59#define CONFIG_CMD_NET 60#define CONFIG_CMD_PCI 61#define CONFIG_CMD_PING 62#define CONFIG_CMD_REGINFO 63#define CONFIG_CMD_USB 64 65#define CONFIG_SLTTMR 66 67#define CONFIG_FSLDMAFEC 68#ifdef CONFIG_FSLDMAFEC 69# define CONFIG_MII 1 70# define CONFIG_MII_INIT 1 71# define CONFIG_HAS_ETH1 72 73# define CONFIG_SYS_DMA_USE_INTSRAM 1 74# define CONFIG_SYS_DISCOVER_PHY 75# define CONFIG_SYS_RX_ETH_BUFFER 32 76# define CONFIG_SYS_TX_ETH_BUFFER 48 77# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 78 79# define CONFIG_SYS_FEC0_PINMUX 0 80# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 81# define CONFIG_SYS_FEC1_PINMUX 0 82# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE 83 84# define MCFFEC_TOUT_LOOP 50000 85/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 86# ifndef CONFIG_SYS_DISCOVER_PHY 87# define FECDUPLEX FULL 88# define FECSPEED _100BASET 89# else 90# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 91# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 92# endif 93# endif /* CONFIG_SYS_DISCOVER_PHY */ 94 95# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 96# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61 97# define CONFIG_IPADDR 192.162.1.2 98# define CONFIG_NETMASK 255.255.255.0 99# define CONFIG_SERVERIP 192.162.1.1 100# define CONFIG_GATEWAYIP 192.162.1.1 101# define CONFIG_OVERWRITE_ETHADDR_ONCE 102 103#endif 104 105#ifdef CONFIG_CMD_USB 106# define CONFIG_USB_STORAGE 107# define CONFIG_DOS_PARTITION 108# define CONFIG_USB_OHCI_NEW 109# ifndef CONFIG_CMD_PCI 110# define CONFIG_CMD_PCI 111# endif 112/*# define CONFIG_PCI_OHCI*/ 113# define CONFIG_SYS_USB_OHCI_REGS_BASE 0x80041000 114# define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 115# define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561" 116# define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 117#endif 118 119/* I2C */ 120#define CONFIG_FSL_I2C 121#define CONFIG_HARD_I2C /* I2C with hw support */ 122#undef CONFIG_SOFT_I2C /* I2C bit-banged */ 123#define CONFIG_SYS_I2C_SPEED 80000 124#define CONFIG_SYS_I2C_SLAVE 0x7F 125#define CONFIG_SYS_I2C_OFFSET 0x00008F00 126#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 127 128/* PCI */ 129#ifdef CONFIG_CMD_PCI 130#define CONFIG_PCI 1 131#define CONFIG_PCI_PNP 1 132#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 133 134#define CONFIG_SYS_PCI_MEM_BUS 0x80000000 135#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS 136#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 137 138#define CONFIG_SYS_PCI_IO_BUS 0x71000000 139#define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS 140#define CONFIG_SYS_PCI_IO_SIZE 0x01000000 141 142#define CONFIG_SYS_PCI_CFG_BUS 0x70000000 143#define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS 144#define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 145#endif 146 147#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 148#define CONFIG_UDP_CHECKSUM 149 150#define CONFIG_HOSTNAME M548xEVB 151#define CONFIG_EXTRA_ENV_SETTINGS \ 152 "netdev=eth0\0" \ 153 "loadaddr=10000\0" \ 154 "u-boot=u-boot.bin\0" \ 155 "load=tftp ${loadaddr) ${u-boot}\0" \ 156 "upd=run load; run prog\0" \ 157 "prog=prot off bank 1;" \ 158 "era ff800000 ff83ffff;" \ 159 "cp.b ${loadaddr} ff800000 ${filesize};"\ 160 "save\0" \ 161 "" 162 163#define CONFIG_PRAM 512 /* 512 KB */ 164#define CONFIG_SYS_PROMPT "-> " 165#define CONFIG_SYS_LONGHELP /* undef to save memory */ 166 167#ifdef CONFIG_CMD_KGDB 168# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 169#else 170# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 171#endif 172 173#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 174#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 175#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 176#define CONFIG_SYS_LOAD_ADDR 0x00010000 177 178#define CONFIG_SYS_HZ 1000 179#define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK 180#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 181 182#define CONFIG_SYS_MBAR 0xF0000000 183#define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000) 184#define CONFIG_SYS_INTSRAMSZ 0x8000 185 186/*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/ 187 188/* 189 * Low Level Configuration Settings 190 * (address mappings, register initial values, etc.) 191 * You should know what you are doing if you make changes here. 192 */ 193/*----------------------------------------------------------------------- 194 * Definitions for initial stack pointer and data area (in DPRAM) 195 */ 196#define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000 197#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ 198#define CONFIG_SYS_INIT_RAM_CTRL 0x21 199#define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) 200#define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */ 201#define CONFIG_SYS_INIT_RAM1_CTRL 0x21 202#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 203#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 204 205/*----------------------------------------------------------------------- 206 * Start addresses for the final memory configuration 207 * (Set up by the startup code) 208 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 209 */ 210#define CONFIG_SYS_SDRAM_BASE 0x00000000 211#define CONFIG_SYS_SDRAM_CFG1 0x73711630 212#define CONFIG_SYS_SDRAM_CFG2 0x46770000 213#define CONFIG_SYS_SDRAM_CTRL 0xE10B0000 214#define CONFIG_SYS_SDRAM_EMOD 0x40010000 215#define CONFIG_SYS_SDRAM_MODE 0x018D0000 216#define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA 217#ifdef CONFIG_SYS_DRAMSZ1 218# define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1) 219#else 220# define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ 221#endif 222 223#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 224#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 225 226#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 227#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 228 229#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 230 231/* Reserve 256 kB for malloc() */ 232#define CONFIG_SYS_MALLOC_LEN (256 << 10) 233/* 234 * For booting Linux, the board info and command line data 235 * have to be in the first 8 MB of memory, since this is 236 * the maximum mapped by the Linux kernel during initialization ?? 237 */ 238#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 239 240/*----------------------------------------------------------------------- 241 * FLASH organization 242 */ 243#define CONFIG_SYS_FLASH_CFI 244#ifdef CONFIG_SYS_FLASH_CFI 245# define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 246# define CONFIG_FLASH_CFI_DRIVER 1 247# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 248# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 249# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 250# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 251#ifdef CONFIG_SYS_NOR1SZ 252# define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 253# define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20) 254# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } 255#else 256# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 257# define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20) 258#endif 259#endif 260 261/* Configuration for environment 262 * Environment is not embedded in u-boot. First time runing may have env 263 * crc error warning if there is no correct environment on the flash. 264 */ 265#define CONFIG_ENV_OFFSET 0x40000 266#define CONFIG_ENV_SECT_SIZE 0x10000 267#define CONFIG_ENV_IS_IN_FLASH 1 268 269/*----------------------------------------------------------------------- 270 * Cache Configuration 271 */ 272#define CONFIG_SYS_CACHELINE_SIZE 16 273 274#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 275 CONFIG_SYS_INIT_RAM_SIZE - 8) 276#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 277 CONFIG_SYS_INIT_RAM_SIZE - 4) 278#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \ 279 CF_CACR_IDCM) 280#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 281#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 282 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 283 CF_ACR_EN | CF_ACR_SM_ALL) 284#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \ 285 CF_CACR_IEC | CF_CACR_ICINVA) 286#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 287 CF_CACR_DEC | CF_CACR_DDCM_P | \ 288 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 289 290/*----------------------------------------------------------------------- 291 * Chipselect bank definitions 292 */ 293/* 294 * CS0 - NOR Flash 1, 2, 4, or 8MB 295 * CS1 - NOR Flash 296 * CS2 - Available 297 * CS3 - Available 298 * CS4 - Available 299 * CS5 - Available 300 */ 301#define CONFIG_SYS_CS0_BASE 0xFF800000 302#define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001) 303#define CONFIG_SYS_CS0_CTRL 0x00101980 304 305#ifdef CONFIG_SYS_NOR1SZ 306#define CONFIG_SYS_CS1_BASE 0xE0000000 307#define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001) 308#define CONFIG_SYS_CS1_CTRL 0x00101D80 309#endif 310 311#endif /* _M5485EVB_H */ 312