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21#ifndef __CONFIG_H
22#define __CONFIG_H
23
24
25
26
27#define CONFIG_E300 1
28#define CONFIG_MPC83xx 1
29#define CONFIG_MPC837x 1
30#define CONFIG_MPC837XEMDS 1
31
32#define CONFIG_SYS_TEXT_BASE 0xFE000000
33
34
35
36
37#ifdef CONFIG_PCISLAVE
38#define CONFIG_83XX_PCICLK 66000000
39#else
40#define CONFIG_83XX_CLKIN 66000000
41#endif
42
43#ifndef CONFIG_SYS_CLK_FREQ
44#define CONFIG_SYS_CLK_FREQ 66000000
45#endif
46
47
48
49
50
51
52#define CONFIG_SYS_HRCW_LOW (\
53 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
54 HRCWL_DDR_TO_SCB_CLK_1X1 |\
55 HRCWL_SVCOD_DIV_2 |\
56 HRCWL_CSB_TO_CLKIN_6X1 |\
57 HRCWL_CORE_TO_CSB_1_5X1)
58
59#ifdef CONFIG_PCISLAVE
60#define CONFIG_SYS_HRCW_HIGH (\
61 HRCWH_PCI_AGENT |\
62 HRCWH_PCI1_ARBITER_DISABLE |\
63 HRCWH_CORE_ENABLE |\
64 HRCWH_FROM_0XFFF00100 |\
65 HRCWH_BOOTSEQ_DISABLE |\
66 HRCWH_SW_WATCHDOG_DISABLE |\
67 HRCWH_ROM_LOC_LOCAL_16BIT |\
68 HRCWH_RL_EXT_LEGACY |\
69 HRCWH_TSEC1M_IN_RGMII |\
70 HRCWH_TSEC2M_IN_RGMII |\
71 HRCWH_BIG_ENDIAN |\
72 HRCWH_LDP_CLEAR)
73#else
74#define CONFIG_SYS_HRCW_HIGH (\
75 HRCWH_PCI_HOST |\
76 HRCWH_PCI1_ARBITER_ENABLE |\
77 HRCWH_CORE_ENABLE |\
78 HRCWH_FROM_0X00000100 |\
79 HRCWH_BOOTSEQ_DISABLE |\
80 HRCWH_SW_WATCHDOG_DISABLE |\
81 HRCWH_ROM_LOC_LOCAL_16BIT |\
82 HRCWH_RL_EXT_LEGACY |\
83 HRCWH_TSEC1M_IN_RGMII |\
84 HRCWH_TSEC2M_IN_RGMII |\
85 HRCWH_BIG_ENDIAN |\
86 HRCWH_LDP_CLEAR)
87#endif
88
89
90#define CONFIG_SYS_ACR_PIPE_DEP 3
91#define CONFIG_SYS_ACR_RPTCNT 3
92
93
94#define CONFIG_SYS_SPCR_TSECEP 3
95
96
97
98
99#define CONFIG_SYS_SCCR_TSEC1CM 1
100#define CONFIG_SYS_SCCR_TSEC2CM 1
101#define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2
102
103
104
105
106#define CONFIG_SYS_SICRH 0x00000000
107#define CONFIG_SYS_SICRL 0x00000000
108
109
110
111
112#define CONFIG_SYS_OBIR 0x31100000
113
114#define CONFIG_BOARD_EARLY_INIT_F
115#define CONFIG_BOARD_EARLY_INIT_R
116#define CONFIG_HWCONFIG
117
118
119
120
121#define CONFIG_SYS_IMMR 0xE0000000
122
123
124
125
126#define CONFIG_SYS_DDR_BASE 0x00000000
127#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
128#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
129#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
130#define CONFIG_SYS_83XX_DDR_USES_CS0
131#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \
132 | DDRCDR_ODT \
133 | DDRCDR_Q_DRN)
134
135
136#undef CONFIG_DDR_ECC
137#undef CONFIG_DDR_ECC_CMD
138
139#define CONFIG_SPD_EEPROM
140#define CONFIG_NEVER_ASSERT_ODT_TO_CPU
141
142#if defined(CONFIG_SPD_EEPROM)
143#define SPD_EEPROM_ADDRESS 0x51
144#else
145
146
147
148
149
150#define CONFIG_SYS_DDR_SIZE 512
151#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
152#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
153 | CSCONFIG_ODT_RD_NEVER \
154 | CSCONFIG_ODT_WR_ONLY_CURRENT \
155 | CSCONFIG_ROW_BIT_14 \
156 | CSCONFIG_COL_BIT_10)
157
158#define CONFIG_SYS_DDR_TIMING_3 0x00000000
159#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
160 | (0 << TIMING_CFG0_WRT_SHIFT) \
161 | (0 << TIMING_CFG0_RRT_SHIFT) \
162 | (0 << TIMING_CFG0_WWT_SHIFT) \
163 | (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
164 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
165 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
166 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
167
168#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
169 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
170 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
171 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
172 | (13 << TIMING_CFG1_REFREC_SHIFT) \
173 | (3 << TIMING_CFG1_WRREC_SHIFT) \
174 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
175 | (2 << TIMING_CFG1_WRTORD_SHIFT))
176
177#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
178 | (6 << TIMING_CFG2_CPO_SHIFT) \
179 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
180 | (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
181 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
182 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
183 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
184
185#define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \
186 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
187
188#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
189#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000
190#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
191 | (0x1432 << SDRAM_MODE_SD_SHIFT))
192
193#define CONFIG_SYS_DDR_MODE2 0x00000000
194#endif
195
196
197
198
199#undef CONFIG_SYS_DRAM_TEST
200#define CONFIG_SYS_MEMTEST_START 0x00040000
201#define CONFIG_SYS_MEMTEST_END 0x00140000
202
203
204
205
206#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
207
208#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
209#define CONFIG_SYS_RAMBOOT
210#else
211#undef CONFIG_SYS_RAMBOOT
212#endif
213
214
215#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
216#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
217
218
219
220
221#define CONFIG_SYS_INIT_RAM_LOCK 1
222#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000
223#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
224#define CONFIG_SYS_GBL_DATA_OFFSET \
225 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
226
227
228
229
230#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
231#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
232#define CONFIG_SYS_LBC_LBCR 0x00000000
233#define CONFIG_FSL_ELBC 1
234
235
236
237
238#define CONFIG_SYS_FLASH_CFI
239#define CONFIG_FLASH_CFI_DRIVER
240#define CONFIG_SYS_FLASH_BASE 0xFE000000
241#define CONFIG_SYS_FLASH_SIZE 32
242#define CONFIG_SYS_FLASH_PROTECTION 1
243
244
245#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
246#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
247
248#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
249 | BR_PS_16 \
250 | BR_MS_GPCM \
251 | BR_V)
252#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
253 | OR_UPM_XAM \
254 | OR_GPCM_CSNT \
255 | OR_GPCM_ACS_DIV2 \
256 | OR_GPCM_XACS \
257 | OR_GPCM_SCY_15 \
258 | OR_GPCM_TRLX_SET \
259 | OR_GPCM_EHTR_SET \
260 | OR_GPCM_EAD)
261
262
263#define CONFIG_SYS_MAX_FLASH_BANKS 1
264#define CONFIG_SYS_MAX_FLASH_SECT 256
265
266#undef CONFIG_SYS_FLASH_CHECKSUM
267#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
268#define CONFIG_SYS_FLASH_WRITE_TOUT 500
269
270
271
272
273#define CONFIG_SYS_BCSR 0xF8000000
274
275#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
276#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
277
278#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
279 | BR_PS_8 \
280 | BR_MS_GPCM \
281 | BR_V)
282
283#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
284 | OR_GPCM_XAM \
285 | OR_GPCM_CSNT \
286 | OR_GPCM_XACS \
287 | OR_GPCM_SCY_15 \
288 | OR_GPCM_TRLX_SET \
289 | OR_GPCM_EHTR_SET \
290 | OR_GPCM_EAD)
291
292
293
294
295
296#define CONFIG_CMD_NAND 1
297#define CONFIG_MTD_NAND_VERIFY_WRITE 1
298#define CONFIG_SYS_MAX_NAND_DEVICE 1
299#define CONFIG_NAND_FSL_ELBC 1
300
301#define CONFIG_SYS_NAND_BASE 0xE0600000
302#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE \
303 | BR_DECC_CHK_GEN \
304 | BR_PS_8 \
305 | BR_MS_FCM \
306 | BR_V)
307#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \
308 | OR_FCM_BCTLD \
309 | OR_FCM_CST \
310 | OR_FCM_CHT \
311 | OR_FCM_SCY_1 \
312 | OR_FCM_RST \
313 | OR_FCM_TRLX \
314 | OR_FCM_EHTR)
315
316
317#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_NAND_BASE
318#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
319
320
321
322
323#define CONFIG_CONS_INDEX 1
324#define CONFIG_SYS_NS16550
325#define CONFIG_SYS_NS16550_SERIAL
326#define CONFIG_SYS_NS16550_REG_SIZE 1
327#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
328
329#define CONFIG_SYS_BAUDRATE_TABLE \
330 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
331
332#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
333#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
334
335
336#define CONFIG_SYS_HUSH_PARSER
337
338
339#define CONFIG_OF_LIBFDT 1
340#define CONFIG_OF_BOARD_SETUP 1
341#define CONFIG_OF_STDOUT_VIA_ALIAS 1
342
343
344#define CONFIG_HARD_I2C
345#undef CONFIG_SOFT_I2C
346#define CONFIG_FSL_I2C
347#define CONFIG_SYS_I2C_SPEED 400000
348#define CONFIG_SYS_I2C_SLAVE 0x7F
349#define CONFIG_SYS_I2C_NOPROBES {0x51}
350#define CONFIG_SYS_I2C_OFFSET 0x3000
351#define CONFIG_SYS_I2C2_OFFSET 0x3100
352
353
354
355
356#define CONFIG_RTC_DS1374
357#define CONFIG_SYS_I2C_RTC_ADDR 0x68
358
359
360
361
362
363#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
364#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
365#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
366#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
367#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
368#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000
369#define CONFIG_SYS_PCI_IO_BASE 0x00000000
370#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
371#define CONFIG_SYS_PCI_IO_SIZE 0x100000
372
373#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
374#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
375#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
376
377#define CONFIG_SYS_PCIE1_BASE 0xA0000000
378#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
379#define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
380#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
381#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
382#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
383#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
384#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
385#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
386
387#define CONFIG_SYS_PCIE2_BASE 0xC0000000
388#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
389#define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
390#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
391#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
392#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
393#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
394#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
395#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
396
397#ifdef CONFIG_PCI
398#ifndef __ASSEMBLY__
399extern int board_pci_host_broken(void);
400#endif
401#define CONFIG_PCIE
402#define CONFIG_PQ_MDS_PIB 1
403
404#define CONFIG_HAS_FSL_DR_USB 1
405
406#define CONFIG_PCI_PNP
407
408#undef CONFIG_EEPRO100
409#undef CONFIG_PCI_SCAN_SHOW
410#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957
411#endif
412
413
414
415
416#define CONFIG_TSEC_ENET
417#define CONFIG_SYS_TSEC1_OFFSET 0x24000
418#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
419#define CONFIG_SYS_TSEC2_OFFSET 0x25000
420#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
421
422
423
424
425#define CONFIG_MII 1
426#define CONFIG_TSEC1 1
427#define CONFIG_TSEC1_NAME "eTSEC0"
428#define CONFIG_TSEC2 1
429#define CONFIG_TSEC2_NAME "eTSEC1"
430#define TSEC1_PHY_ADDR 2
431#define TSEC2_PHY_ADDR 3
432#define TSEC1_PHY_ADDR_SGMII 8
433#define TSEC2_PHY_ADDR_SGMII 4
434#define TSEC1_PHYIDX 0
435#define TSEC2_PHYIDX 0
436#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
437#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
438
439
440#define CONFIG_ETHPRIME "eTSEC1"
441
442
443#define CONFIG_FSL_SERDES
444#define CONFIG_FSL_SERDES1 0xe3000
445#define CONFIG_FSL_SERDES2 0xe3100
446
447
448
449
450#define CONFIG_LIBATA
451#define CONFIG_FSL_SATA
452
453#define CONFIG_SYS_SATA_MAX_DEVICE 2
454#define CONFIG_SATA1
455#define CONFIG_SYS_SATA1_OFFSET 0x18000
456#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
457#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
458#define CONFIG_SATA2
459#define CONFIG_SYS_SATA2_OFFSET 0x19000
460#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
461#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
462
463#ifdef CONFIG_FSL_SATA
464#define CONFIG_LBA48
465#define CONFIG_CMD_SATA
466#define CONFIG_DOS_PARTITION
467#define CONFIG_CMD_EXT2
468#endif
469
470
471
472
473#ifndef CONFIG_SYS_RAMBOOT
474 #define CONFIG_ENV_IS_IN_FLASH 1
475 #define CONFIG_ENV_ADDR \
476 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
477 #define CONFIG_ENV_SECT_SIZE 0x20000
478 #define CONFIG_ENV_SIZE 0x2000
479#else
480 #define CONFIG_SYS_NO_FLASH 1
481 #define CONFIG_ENV_IS_NOWHERE 1
482 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
483 #define CONFIG_ENV_SIZE 0x2000
484#endif
485
486#define CONFIG_LOADS_ECHO 1
487#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
488
489
490
491
492#define CONFIG_BOOTP_BOOTFILESIZE
493#define CONFIG_BOOTP_BOOTPATH
494#define CONFIG_BOOTP_GATEWAY
495#define CONFIG_BOOTP_HOSTNAME
496
497
498
499
500
501#include <config_cmd_default.h>
502
503#define CONFIG_CMD_PING
504#define CONFIG_CMD_I2C
505#define CONFIG_CMD_MII
506#define CONFIG_CMD_DATE
507
508#if defined(CONFIG_PCI)
509 #define CONFIG_CMD_PCI
510#endif
511
512#if defined(CONFIG_SYS_RAMBOOT)
513 #undef CONFIG_CMD_SAVEENV
514 #undef CONFIG_CMD_LOADS
515#endif
516
517#define CONFIG_CMDLINE_EDITING 1
518#define CONFIG_AUTO_COMPLETE
519
520#undef CONFIG_WATCHDOG
521
522#define CONFIG_MMC 1
523
524#ifdef CONFIG_MMC
525#define CONFIG_FSL_ESDHC
526#define CONFIG_FSL_ESDHC_PIN_MUX
527#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
528#define CONFIG_CMD_MMC
529#define CONFIG_GENERIC_MMC
530#define CONFIG_CMD_EXT2
531#define CONFIG_CMD_FAT
532#define CONFIG_DOS_PARTITION
533#endif
534
535
536
537
538#define CONFIG_SYS_LONGHELP
539#define CONFIG_SYS_LOAD_ADDR 0x2000000
540#define CONFIG_SYS_PROMPT "=> "
541
542#if defined(CONFIG_CMD_KGDB)
543 #define CONFIG_SYS_CBSIZE 1024
544#else
545 #define CONFIG_SYS_CBSIZE 256
546#endif
547
548
549#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
550#define CONFIG_SYS_MAXARGS 16
551
552#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
553#define CONFIG_SYS_HZ 1000
554
555
556
557
558
559
560#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
561
562
563
564
565#define CONFIG_SYS_HID0_INIT 0x000000000
566#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
567 HID0_ENABLE_INSTRUCTION_CACHE)
568#define CONFIG_SYS_HID2 HID2_HBE
569
570
571
572
573#define CONFIG_HIGH_BATS 1
574
575
576#define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE
577#define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000)
578
579#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \
580 | BATL_PP_RW \
581 | BATL_MEMCOHERENCE)
582#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \
583 | BATU_BL_256M \
584 | BATU_VS \
585 | BATU_VP)
586#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
587#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
588
589#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \
590 | BATL_PP_RW \
591 | BATL_MEMCOHERENCE)
592#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \
593 | BATU_BL_256M \
594 | BATU_VS \
595 | BATU_VP)
596#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
597#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
598
599
600#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \
601 | BATL_PP_RW \
602 | BATL_CACHEINHIBIT \
603 | BATL_GUARDEDSTORAGE)
604#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \
605 | BATU_BL_8M \
606 | BATU_VS \
607 | BATU_VP)
608#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
609#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
610
611
612#define CONFIG_SYS_IBAT3L (CONFIG_SYS_BCSR \
613 | BATL_PP_RW \
614 | BATL_CACHEINHIBIT \
615 | BATL_GUARDEDSTORAGE)
616#define CONFIG_SYS_IBAT3U (CONFIG_SYS_BCSR \
617 | BATU_BL_128K \
618 | BATU_VS \
619 | BATU_VP)
620#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
621#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
622
623
624#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \
625 | BATL_PP_RW \
626 | BATL_MEMCOHERENCE)
627#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \
628 | BATU_BL_32M \
629 | BATU_VS \
630 | BATU_VP)
631#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \
632 | BATL_PP_RW \
633 | BATL_CACHEINHIBIT \
634 | BATL_GUARDEDSTORAGE)
635#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
636
637
638#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
639#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
640 | BATU_BL_128K \
641 | BATU_VS \
642 | BATU_VP)
643#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
644#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
645
646#ifdef CONFIG_PCI
647
648#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \
649 | BATL_PP_RW \
650 | BATL_MEMCOHERENCE)
651#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \
652 | BATU_BL_256M \
653 | BATU_VS \
654 | BATU_VP)
655#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
656#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
657
658#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \
659 | BATL_PP_RW \
660 | BATL_CACHEINHIBIT \
661 | BATL_GUARDEDSTORAGE)
662#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \
663 | BATU_BL_256M \
664 | BATU_VS \
665 | BATU_VP)
666#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
667#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
668#else
669#define CONFIG_SYS_IBAT6L (0)
670#define CONFIG_SYS_IBAT6U (0)
671#define CONFIG_SYS_IBAT7L (0)
672#define CONFIG_SYS_IBAT7U (0)
673#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
674#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
675#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
676#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
677#endif
678
679#if defined(CONFIG_CMD_KGDB)
680#define CONFIG_KGDB_BAUDRATE 230400
681#define CONFIG_KGDB_SER_INDEX 2
682#endif
683
684
685
686
687
688#define CONFIG_ENV_OVERWRITE
689
690#if defined(CONFIG_TSEC_ENET)
691#define CONFIG_HAS_ETH0
692#define CONFIG_HAS_ETH1
693#endif
694
695#define CONFIG_BAUDRATE 115200
696
697#define CONFIG_LOADADDR 800000
698
699#define CONFIG_BOOTDELAY 6
700#undef CONFIG_BOOTARGS
701
702#define CONFIG_EXTRA_ENV_SETTINGS \
703 "netdev=eth0\0" \
704 "consoledev=ttyS0\0" \
705 "ramdiskaddr=1000000\0" \
706 "ramdiskfile=ramfs.83xx\0" \
707 "fdtaddr=780000\0" \
708 "fdtfile=mpc8379_mds.dtb\0" \
709 ""
710
711#define CONFIG_NFSBOOTCOMMAND \
712 "setenv bootargs root=/dev/nfs rw " \
713 "nfsroot=$serverip:$rootpath " \
714 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
715 "$netdev:off " \
716 "console=$consoledev,$baudrate $othbootargs;" \
717 "tftp $loadaddr $bootfile;" \
718 "tftp $fdtaddr $fdtfile;" \
719 "bootm $loadaddr - $fdtaddr"
720
721#define CONFIG_RAMBOOTCOMMAND \
722 "setenv bootargs root=/dev/ram rw " \
723 "console=$consoledev,$baudrate $othbootargs;" \
724 "tftp $ramdiskaddr $ramdiskfile;" \
725 "tftp $loadaddr $bootfile;" \
726 "tftp $fdtaddr $fdtfile;" \
727 "bootm $loadaddr $ramdiskaddr $fdtaddr"
728
729
730#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
731
732#endif
733