LXR uboot/include/configs/P2020COME.h

   1/*
   2 * Copyright 2009-2010,2012 Freescale Semiconductor, Inc.
   3 *
   4 * See file CREDITS for list of people who contributed to this
   5 * project.
   6 *
   7 * This program is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU General Public License as
   9 * published by the Free Software Foundation; either version 2 of
  10 * the License, or (at your option) any later version.
  11 *
  12 * This program is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
  15 * GNU General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU General Public License
  18 * along with this program; if not, write to the Free Software
  19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20 * MA 02111-1307 USA
  21 */
  22
  23#ifndef __CONFIG_H
  24#define __CONFIG_H
  25
  26/* The P2020COME board is only booted via the Freescale On-Chip ROM */
  27#define CONFIG_SYS_RAMBOOT
  28#define CONFIG_SYS_EXTRA_ENV_RELOC
  29
  30#define CONFIG_SYS_TEXT_BASE            0xf8f80000
  31#define CONFIG_RESET_VECTOR_ADDRESS     0xf8fffffc
  32
  33#ifdef CONFIG_SDCARD
  34#define CONFIG_RAMBOOT_SDCARD           1
  35#endif
  36
  37#ifdef CONFIG_SPIFLASH
  38#define CONFIG_RAMBOOT_SPIFLASH         1
  39#endif
  40
  41#ifndef CONFIG_SYS_MONITOR_BASE
  42#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  43#endif
  44
  45/* High Level Configuration Options */
  46#define CONFIG_BOOKE            1       /* BOOKE */
  47#define CONFIG_E500             1       /* BOOKE e500 family */
  48#define CONFIG_MPC85xx          1       /* MPC8540/60/55/41/48/P1020/P2020,etc*/
  49#define CONFIG_P2020            1
  50#define CONFIG_P2020COME        1
  51#define CONFIG_FSL_ELBC         1       /* Enable eLBC Support */
  52#define CONFIG_MP
  53
  54#define CONFIG_PCI              1       /* Enable PCI/PCIE */
  55#if defined(CONFIG_PCI)
  56#define CONFIG_PCIE1            1       /* PCIE controller 1 (slot 1) */
  57#define CONFIG_PCIE2            1       /* PCIE controller 2 (slot 2) */
  58#define CONFIG_PCIE3            1       /* PCIE controller 3 (slot 3) */
  59
  60#define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  61#define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  62#define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  63#endif /* #if defined(CONFIG_PCI) */
  64#define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  65#define CONFIG_TSEC_ENET                /* tsec ethernet support */
  66#define CONFIG_ENV_OVERWRITE
  67
  68#if defined(CONFIG_PCI)
  69#define CONFIG_E1000            1       /* E1000 pci Ethernet card */
  70#endif
  71
  72#ifndef __ASSEMBLY__
  73extern unsigned long get_board_ddr_clk(unsigned long dummy);
  74extern unsigned long get_board_sys_clk(unsigned long dummy);
  75#endif
  76
  77/*
  78 * For P2020COME DDRCLK and SYSCLK are from the same oscillator
  79 * For DA phase the SYSCLK is 66MHz
  80 * For EA phase the SYSCLK is 100MHz
  81 */
  82#define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk(0)
  83#define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
  84
  85#define CONFIG_HWCONFIG
  86
  87/*
  88 * These can be toggled for performance analysis, otherwise use default.
  89 */
  90#define CONFIG_L2_CACHE                 /* toggle L2 cache */
  91#define CONFIG_BTB                      /* toggle branch prediction */
  92
  93#define CONFIG_ADDR_STREAMING           /* toggle addr streaming */
  94
  95#define CONFIG_ENABLE_36BIT_PHYS        1
  96
  97#ifdef CONFIG_PHYS_64BIT
  98#define CONFIG_ADDR_MAP                 1
  99#define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
 100#endif
 101
 102#define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest works on */
 103#define CONFIG_SYS_MEMTEST_END          0x1fffffff
 104#define CONFIG_PANIC_HANG       /* do not reset board on panic */
 105
 106 /*
 107  * Config the L2 Cache as L2 SRAM
 108  */
 109#define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 110#ifdef CONFIG_PHYS_64BIT
 111#define CONFIG_SYS_INIT_L2_ADDR_PHYS    0xff8f80000ull
 112#else
 113#define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 114#endif
 115#define CONFIG_SYS_L2_SIZE              (512 << 10)
 116#define CONFIG_SYS_INIT_L2_END          (CONFIG_SYS_INIT_L2_ADDR \
 117                                        + CONFIG_SYS_L2_SIZE)
 118
 119#define CONFIG_SYS_CCSRBAR              0xffe00000
 120#define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
 121
 122/* DDR Setup */
 123#define CONFIG_FSL_DDR3
 124#define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
 125#define CONFIG_DDR_SPD
 126
 127#define CONFIG_DDR_ECC
 128#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 129#define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 130
 131#define CONFIG_SYS_SDRAM_SIZE           2048ULL /* DDR size on P2020COME */
 132#define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 133#define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 134
 135#define CONFIG_NUM_DDR_CONTROLLERS      1
 136#define CONFIG_DIMM_SLOTS_PER_CTLR      1
 137#define CONFIG_CHIP_SELECTS_PER_CTRL    2
 138
 139#define CONFIG_SYS_DDR_ERR_INT_EN       0x0000000d
 140#define CONFIG_SYS_DDR_ERR_DIS          0x00000000
 141#define CONFIG_SYS_DDR_SBE              0x00ff0000
 142
 143#define CONFIG_SYS_SPD_BUS_NUM          1
 144#define SPD_EEPROM_ADDRESS              0x53
 145
 146/*
 147 * Memory map
 148 *
 149 * 0x0000_0000  0x7fff_ffff     DDR3                    2G Cacheable
 150 * 0x8000_0000  0x9fff_ffff     PCI Express 3 Mem       1G non-cacheable
 151 * 0xa000_0000  0xbfff_ffff     PCI Express 2 Mem       1G non-cacheable
 152 * 0xc000_0000  0xdfff_ffff     PCI Express 1 Mem       1G non-cacheable
 153 * 0xffc1_0000  0xffc1_ffff     PCI Express 3 IO        64K non-cacheable
 154 * 0xffc2_0000  0xffc2_ffff     PCI Express 2 IO        64K non-cacheable
 155 * 0xffc3_0000  0xffc3_ffff     PCI Express 1 IO        64K non-cacheable
 156 *
 157 * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 158 * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 159 */
 160
 161/*
 162 * Local Bus Definitions
 163 */
 164
 165/* There is no NOR Flash on P2020COME */
 166#define CONFIG_SYS_NO_FLASH
 167
 168#define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 169#define CONFIG_HWCONFIG
 170
 171#define CONFIG_SYS_INIT_RAM_LOCK        1
 172#define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* stack in RAM */
 173#ifdef CONFIG_PHYS_64BIT
 174#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 175#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       CONFIG_SYS_INIT_RAM_ADDR
 176/* the assembler doesn't like typecast */
 177#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 178        ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 179          CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 180#else
 181#define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR
 182#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 183#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 184#endif
 185#define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 186
 187#define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE \
 188                                                - GENERATED_GBL_DATA_SIZE)
 189#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 190
 191#define CONFIG_SYS_MONITOR_LEN          (256 * 1024)
 192#define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)
 193
 194/* Serial Port - controlled on board with jumper J8
 195 * open - index 2
 196 * shorted - index 1
 197 */
 198#define CONFIG_CONS_INDEX               1
 199#define CONFIG_SYS_NS16550
 200#define CONFIG_SYS_NS16550_SERIAL
 201#define CONFIG_SYS_NS16550_REG_SIZE     1
 202#define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 203
 204#define CONFIG_SERIAL_MULTI     1 /* Enable both serial ports */
 205#define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* determine from environment */
 206
 207#define CONFIG_SYS_BAUDRATE_TABLE   \
 208        {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 209
 210#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 211#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 212
 213/* Use the HUSH parser */
 214#define CONFIG_SYS_HUSH_PARSER
 215
 216/*
 217 * Pass open firmware flat tree
 218 */
 219#define CONFIG_OF_LIBFDT                1
 220#define CONFIG_OF_BOARD_SETUP           1
 221#define CONFIG_OF_STDOUT_VIA_ALIAS      1
 222
 223/* new uImage format support */
 224#define CONFIG_FIT                      1
 225#define CONFIG_FIT_VERBOSE              1
 226
 227/* I2C */
 228#define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 229#define CONFIG_HARD_I2C         /* I2C with hardware support */
 230#undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
 231#define CONFIG_I2C_MULTI_BUS
 232#define CONFIG_I2C_CMD_TREE
 233#define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address*/
 234#define CONFIG_SYS_I2C_SLAVE            0x7F
 235#define CONFIG_SYS_I2C_NOPROBES         { {0, 0x29} }
 236#define CONFIG_SYS_I2C_OFFSET           0x3000
 237#define CONFIG_SYS_I2C2_OFFSET          0x3100
 238
 239/*
 240 * I2C2 EEPROM
 241 */
 242#define CONFIG_ID_EEPROM
 243#ifdef CONFIG_ID_EEPROM
 244#define CONFIG_SYS_I2C_EEPROM_NXID
 245#endif
 246#define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 247#define CONFIG_SYS_I2C_EEPROM_ADDR2     0x18
 248#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 249#define CONFIG_SYS_EEPROM_BUS_NUM       0
 250#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10 /* and takes up to 10 msec */
 251
 252/*
 253 * eSPI - Enhanced SPI
 254 */
 255#define CONFIG_FSL_ESPI
 256#define CONFIG_SPI_FLASH
 257#define CONFIG_SPI_FLASH_STMICRO
 258#define CONFIG_CMD_SF
 259#define CONFIG_SF_DEFAULT_SPEED         10000000
 260#define CONFIG_SF_DEFAULT_MODE          SPI_MODE_0
 261
 262/*
 263 * General PCI
 264 * Memory space is mapped 1-1, but I/O space must start from 0.
 265 */
 266#if defined(CONFIG_PCI)
 267
 268/* controller 3, Slot 3, tgtid 3, Base address 8000 */
 269#define CONFIG_SYS_PCIE3_MEM_VIRT       0x80000000
 270#define CONFIG_SYS_PCIE3_MEM_BUS        0x80000000
 271#define CONFIG_SYS_PCIE3_MEM_PHYS       0x80000000
 272#define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000  /* 512M */
 273#define CONFIG_SYS_PCIE3_IO_VIRT        0xffc10000
 274#define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 275#define CONFIG_SYS_PCIE3_IO_PHYS        0xffc10000
 276#define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000  /* 64k */
 277
 278/* controller 2, Slot 2, tgtid 2, Base address 9000 */
 279#define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 280#define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 281#define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 282#define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000  /* 512M */
 283#define CONFIG_SYS_PCIE2_IO_VIRT        0xffc20000
 284#define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 285#define CONFIG_SYS_PCIE2_IO_PHYS        0xffc20000
 286#define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000  /* 64k */
 287
 288/* controller 1, Slot 1, tgtid 1, Base address a000 */
 289#define CONFIG_SYS_PCIE1_MEM_VIRT       0xc0000000
 290#define CONFIG_SYS_PCIE1_MEM_BUS        0xc0000000
 291#define CONFIG_SYS_PCIE1_MEM_PHYS       0xc0000000
 292#define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000  /* 512M */
 293#define CONFIG_SYS_PCIE1_IO_VIRT        0xffc30000
 294#define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 295#define CONFIG_SYS_PCIE1_IO_PHYS        0xffc30000
 296#define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000  /* 64k */
 297
 298#define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 299
 300#undef CONFIG_EEPRO100
 301#undef CONFIG_TULIP
 302#undef CONFIG_RTL8139
 303
 304#ifdef CONFIG_RTL8139
 305/* This macro is used by RTL8139 but not defined in PPC architecture */
 306#define KSEG1ADDR(x)            (x)
 307#define _IO_BASE                0x00000000
 308#endif
 309
 310#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 311#define CONFIG_DOS_PARTITION
 312
 313#endif  /* CONFIG_PCI */
 314
 315#if defined(CONFIG_TSEC_ENET)
 316#define CONFIG_MII              1       /* MII PHY management */
 317#define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 318#define CONFIG_TSEC1            1
 319#define CONFIG_TSEC1_NAME       "eTSEC1"
 320#define CONFIG_TSEC2            1
 321#define CONFIG_TSEC2_NAME       "eTSEC2"
 322#define CONFIG_TSEC3            1
 323#define CONFIG_TSEC3_NAME       "eTSEC3"
 324
 325#define TSEC1_PHY_ADDR          0
 326#define TSEC2_PHY_ADDR          2
 327#define TSEC3_PHY_ADDR          1
 328
 329#undef CONFIG_VSC7385_ENET
 330
 331#define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 332#define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 333#define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 334
 335#define TSEC1_PHYIDX            0
 336#define TSEC2_PHYIDX            0
 337#define TSEC3_PHYIDX            0
 338
 339#define CONFIG_ETHPRIME         "eTSEC1"
 340
 341#define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 342
 343#endif  /* CONFIG_TSEC_ENET */
 344
 345/*
 346 * Environment
 347 */
 348#if defined(CONFIG_RAMBOOT_SDCARD)
 349        #define CONFIG_ENV_IS_IN_MMC    1
 350        #define CONFIG_FSL_FIXED_MMC_LOCATION
 351        #define CONFIG_ENV_SIZE         0x2000
 352        #define CONFIG_SYS_MMC_ENV_DEV  0
 353#elif defined(CONFIG_RAMBOOT_SPIFLASH)
 354        #define CONFIG_ENV_IS_IN_SPI_FLASH
 355        #define CONFIG_ENV_SPI_BUS      0
 356        #define CONFIG_ENV_SPI_CS       0
 357        #define CONFIG_ENV_SPI_MAX_HZ   10000000
 358        #define CONFIG_ENV_SPI_MODE     0
 359        #define CONFIG_ENV_OFFSET       0x100000        /* 1MB */
 360        #define CONFIG_ENV_SECT_SIZE    0x10000
 361        #define CONFIG_ENV_SIZE         0x2000
 362#endif
 363
 364#define CONFIG_LOADS_ECHO               1
 365#define CONFIG_SYS_LOADS_BAUD_CHANGE    1
 366
 367/*
 368 * Command line configuration.
 369 */
 370#include <config_cmd_default.h>
 371
 372#define CONFIG_CMD_ELF
 373#define CONFIG_CMD_I2C
 374#define CONFIG_CMD_IRQ
 375#define CONFIG_CMD_MII
 376#define CONFIG_CMD_PING
 377#define CONFIG_CMD_SETEXPR
 378#define CONFIG_CMD_REGINFO
 379
 380#if defined(CONFIG_PCI)
 381#define CONFIG_CMD_NET
 382#define CONFIG_CMD_PCI
 383#endif
 384
 385#undef CONFIG_WATCHDOG                  /* watchdog disabled */
 386
 387#define CONFIG_MMC      1
 388
 389#ifdef CONFIG_MMC
 390#define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init */
 391#define CONFIG_CMD_MMC
 392#define CONFIG_DOS_PARTITION
 393#define CONFIG_FSL_ESDHC
 394#define CONFIG_GENERIC_MMC
 395#define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 396#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 397#endif /* CONFIG_MMC */
 398
 399#define CONFIG_HAS_FSL_DR_USB
 400#ifdef CONFIG_HAS_FSL_DR_USB
 401#define CONFIG_USB_EHCI
 402
 403#ifdef CONFIG_USB_EHCI
 404#define CONFIG_CMD_USB
 405#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 406#define CONFIG_USB_EHCI_FSL
 407#define CONFIG_USB_STORAGE
 408#endif
 409#endif
 410
 411#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
 412#define CONFIG_CMD_EXT2
 413#define CONFIG_CMD_FAT
 414#define CONFIG_DOS_PARTITION
 415#endif
 416
 417/* Misc Extra Settings */
 418#define CONFIG_CMD_DHCP                 1
 419
 420#define CONFIG_CMD_DATE                 1
 421#define CONFIG_RTC_M41T62               1
 422#define CONFIG_SYS_RTC_BUS_NUM          1
 423#define CONFIG_SYS_I2C_RTC_ADDR         0x68
 424
 425/*
 426 * Miscellaneous configurable options
 427 */
 428#define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 429#define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 430#define CONFIG_AUTO_COMPLETE    1               /* add autocompletion support */
 431#define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 432#define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 433#if defined(CONFIG_CMD_KGDB)
 434#define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 435#else
 436#define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 437#endif
 438#define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 439                                                /* Print Buffer Size */
 440#define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 441#define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 442#define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms tick */
 443
 444/*
 445 * For booting Linux, the board info and command line data
 446 * have to be in the first 64 MB of memory, since this is
 447 * the maximum mapped by the Linux kernel during initialization.
 448 */
 449#define CONFIG_SYS_BOOTMAPSZ    (64 << 20)
 450#define CONFIG_SYS_BOOTM_LEN    (64 << 20)
 451
 452#if defined(CONFIG_CMD_KGDB)
 453#define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 454#define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 455#endif
 456
 457/*
 458 * Environment Configuration
 459 */
 460
 461/* The mac addresses for all ethernet interface */
 462#if defined(CONFIG_TSEC_ENET)
 463#define CONFIG_HAS_ETH0
 464#define CONFIG_HAS_ETH1
 465#define CONFIG_HAS_ETH2
 466#define CONFIG_HAS_ETH3
 467#endif
 468
 469#define CONFIG_HOSTNAME         unknown
 470#define CONFIG_ROOTPATH         "/opt/nfsroot"
 471#define CONFIG_BOOTFILE         "uImage"
 472#define CONFIG_UBOOTPATH        u-boot.bin
 473
 474/* default location for tftp and bootm */
 475#define CONFIG_LOADADDR         1000000
 476
 477#define CONFIG_BOOTDELAY        10      /* -1 disables auto-boot */
 478#undef  CONFIG_BOOTARGS                 /* the boot command will set bootargs */
 479
 480#define CONFIG_BAUDRATE         115200
 481
 482#define CONFIG_EXTRA_ENV_SETTINGS                                       \
 483        "hwconfig=fsl_ddr:ecc=on\0"                                     \
 484        "bootcmd=run sdboot\0"                                          \
 485        "sdboot=setenv bootargs root=/dev/mmcblk0p2 rw "                \
 486                "rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\
 487                "$othbootargs; mmcinfo; "                               \
 488                "ext2load mmc 0:2 $loadaddr /boot/$bootfile; "          \
 489                "ext2load mmc 0:2 $fdtaddr /boot/$fdtfile; "            \
 490                "bootm $loadaddr - $fdtaddr\0"                          \
 491        "sdfatboot=setenv bootargs root=/dev/ram rw "                   \
 492                "rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\
 493                "$othbootargs; mmcinfo; "                               \
 494                "fatload mmc 0:1 $loadaddr $bootfile; "                 \
 495                "fatload mmc 0:1 $fdtaddr $fdtfile; "                   \
 496                "fatload mmc 0:1 $ramdiskaddr $ramdiskfile; "           \
 497                "bootm $loadaddr $ramdiskaddr $fdtaddr\0"               \
 498        "usbboot=setenv bootargs root=/dev/sda1 rw "                    \
 499                "rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\
 500                "$othbootargs; "                                        \
 501                "usb start; "                                           \
 502                "ext2load usb 0:1 $loadaddr /boot/$bootfile; "          \
 503                "ext2load usb 0:1 $fdtaddr /boot/$fdtfile; "            \
 504                "bootm $loadaddr - $fdtaddr\0"                          \
 505        "usbfatboot=setenv bootargs root=/dev/ram rw "                  \
 506                "console=$consoledev,$baudrate $othbootargs; "          \
 507                "usb start; "                                           \
 508                "fatload usb 0:2 $loadaddr $bootfile; "                 \
 509                "fatload usb 0:2 $fdtaddr $fdtfile; "                   \
 510                "fatload usb 0:2 $ramdiskaddr $ramdiskfile; "           \
 511                "bootm $loadaddr $ramdiskaddr $fdtaddr\0"               \
 512        "usbext2boot=setenv bootargs root=/dev/ram rw "                 \
 513                "console=$consoledev,$baudrate $othbootargs; "          \
 514                "usb start; "                                           \
 515                "ext2load usb 0:4 $loadaddr $bootfile; "                \
 516                "ext2load usb 0:4 $fdtaddr $fdtfile; "                  \
 517                "ext2load usb 0:4 $ramdiskaddr $ramdiskfile; "          \
 518                "bootm $loadaddr $ramdiskaddr $fdtaddr\0"               \
 519        "upgradespi=sf probe 0; "                                       \
 520                "setenv startaddr 0; "                                  \
 521                "setenv erasesize a0000; "                              \
 522                "tftp 1000000 $tftppath/$uboot_spi; "                   \
 523                "sf erase $startaddr $erasesize; "                      \
 524                "sf write 1000000 $startaddr $filesize; "               \
 525                "sf erase 100000 120000\0"                              \
 526        "clearspienv=sf probe 0;sf erase 100000 20000\0"                \
 527        "othbootargs=ramdisk_size=700000 cache-sram-size=0x10000\0"     \
 528        "netdev=eth0\0"                                                 \
 529        "rootdelaysecond=15\0"                                          \
 530        "uboot_nor=u-boot-nor.bin\0"                                    \
 531        "uboot_spi=u-boot-p2020.spi\0"                                  \
 532        "uboot_sd=u-boot-p2020.bin\0"                                   \
 533        "consoledev=ttyS0\0"                                            \
 534        "ramdiskaddr=2000000\0"                                         \
 535        "ramdiskfile=rootfs-dev.ext2.img\0"                             \
 536        "fdtaddr=c00000\0"                                              \
 537        "fdtfile=uImage-2.6.32-p2020.dtb\0"                             \
 538        "tftppath=p2020\0"
 539
 540#define CONFIG_HDBOOT                                                   \
 541        "setenv bootargs root=/dev/$bdev rw rootdelay=30 "              \
 542        "console=$consoledev,$baudrate $othbootargs;"                   \
 543        "usb start;"                                                    \
 544        "ext2load usb 0:1 $loadaddr /boot/$bootfile;"                   \
 545        "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"                     \
 546        "bootm $loadaddr - $fdtaddr"
 547
 548#define CONFIG_NFSBOOTCOMMAND                                           \
 549        "setenv bootargs root=/dev/nfs rw "                             \
 550        "nfsroot=$serverip:$rootpath "                                  \
 551        "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
 552        "console=$consoledev,$baudrate $othbootargs;"                   \
 553        "tftp $loadaddr $tftppath/$bootfile;"                           \
 554        "tftp $fdtaddr $tftppath/$fdtfile;"                             \
 555        "bootm $loadaddr - $fdtaddr"
 556
 557
 558#define CONFIG_RAMBOOTCOMMAND                                           \
 559        "setenv bootargs root=/dev/ram rw "                             \
 560        "console=$consoledev,$baudrate $othbootargs;"                   \
 561        "tftp $ramdiskaddr $tftppath/$ramdiskfile;"                     \
 562        "tftp $loadaddr $tftppath/$bootfile;"                           \
 563        "tftp $fdtaddr $tftppath/$fdtfile;"                             \
 564        "bootm $loadaddr $ramdiskaddr $fdtaddr"
 565
 566#define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 567
 568#endif  /* __CONFIG_H */
 569