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33
34#ifndef __CONFIG_H
35#define __CONFIG_H
36
37#define CONFIG_PPCHAMELEON_MODULE_BA 0
38#define CONFIG_PPCHAMELEON_MODULE_ME 1
39#define CONFIG_PPCHAMELEON_MODULE_HI 2
40#ifndef CONFIG_PPCHAMELEON_MODULE_MODEL
41#define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA
42#endif
43
44
45
46
47
48
49#if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33))
50#define CONFIG_PPCHAMELEON_CLK_25
51#endif
52
53#if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33))
54#error "* Two external frequencies (SysClk) are defined! *"
55#endif
56
57#undef CONFIG_PPCHAMELEON_SMI712
58
59
60
61
62#undef __DEBUG_START_FROM_SRAM__
63#define __DISABLE_MACHINE_EXCEPTION__
64
65#ifdef __DEBUG_START_FROM_SRAM__
66#define CONFIG_SYS_DUMMY_FLASH_SIZE 1024*1024*4
67#endif
68
69
70
71
72
73
74#define CONFIG_405EP 1
75#define CONFIG_4xx 1
76#define CONFIG_PPCHAMELEONEVB 1
77
78#define CONFIG_SYS_TEXT_BASE 0xFFFB0000
79#define CONFIG_SYS_LDSCRIPT "board/dave/PPChameleonEVB/u-boot.lds"
80
81#define CONFIG_BOARD_EARLY_INIT_F 1
82#define CONFIG_MISC_INIT_R 1
83
84
85#ifdef CONFIG_PPCHAMELEON_CLK_25
86# define CONFIG_SYS_CLK_FREQ 25000000
87#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
88# define CONFIG_SYS_CLK_FREQ 33333333
89#else
90# error "* External frequency (SysClk) not defined! *"
91#endif
92
93#define CONFIG_BAUDRATE 115200
94#define CONFIG_BOOTDELAY 5
95
96#undef CONFIG_BOOTARGS
97
98
99#define CONFIG_ENV_OVERWRITE
100#define CONFIG_ETHADDR 00:50:c2:1e:af:fe
101#define CONFIG_HAS_ETH1
102#define CONFIG_ETH1ADDR 00:50:c2:1e:af:fd
103
104#define CONFIG_LOADS_ECHO 1
105#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
106
107#undef CONFIG_EXT_PHY
108
109#define CONFIG_PPC4xx_EMAC
110#define CONFIG_MII 1
111#ifndef CONFIG_EXT_PHY
112#define CONFIG_PHY_ADDR 1
113#define CONFIG_PHY1_ADDR 2
114#else
115#define CONFIG_PHY_ADDR 2
116#endif
117#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
118
119
120
121
122
123#define CONFIG_BOOTP_BOOTFILESIZE
124#define CONFIG_BOOTP_BOOTPATH
125#define CONFIG_BOOTP_GATEWAY
126#define CONFIG_BOOTP_HOSTNAME
127
128
129
130
131
132#include <config_cmd_default.h>
133
134#define CONFIG_CMD_DATE
135#define CONFIG_CMD_DHCP
136#define CONFIG_CMD_ELF
137#define CONFIG_CMD_EEPROM
138#define CONFIG_CMD_I2C
139#define CONFIG_CMD_IRQ
140#define CONFIG_CMD_JFFS2
141#define CONFIG_CMD_MII
142#define CONFIG_CMD_NAND
143#define CONFIG_CMD_NFS
144#define CONFIG_CMD_PCI
145#define CONFIG_CMD_SNTP
146
147
148#define CONFIG_MAC_PARTITION
149#define CONFIG_DOS_PARTITION
150
151#undef CONFIG_WATCHDOG
152
153#define CONFIG_RTC_M41T11 1
154#define CONFIG_SYS_I2C_RTC_ADDR 0x68
155#define CONFIG_SYS_M41T11_BASE_YEAR 1900
156
157
158
159
160#define CONFIG_SDRAM_BANK0 1
161
162
163#define CONFIG_SYS_SDRAM_CL 2
164#define CONFIG_SYS_SDRAM_tRP 20
165#define CONFIG_SYS_SDRAM_tRC 65
166#define CONFIG_SYS_SDRAM_tRCD 20
167#undef CONFIG_SYS_SDRAM_tRFC
168
169
170
171
172#define CONFIG_SYS_LONGHELP
173#define CONFIG_SYS_PROMPT "=> "
174
175#undef CONFIG_SYS_HUSH_PARSER
176
177#if defined(CONFIG_CMD_KGDB)
178#define CONFIG_SYS_CBSIZE 1024
179#else
180#define CONFIG_SYS_CBSIZE 256
181#endif
182#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
183#define CONFIG_SYS_MAXARGS 16
184#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
185
186#define CONFIG_SYS_DEVICE_NULLDEV 1
187
188#define CONFIG_SYS_CONSOLE_INFO_QUIET 1
189
190#define CONFIG_SYS_MEMTEST_START 0x0400000
191#define CONFIG_SYS_MEMTEST_END 0x0C00000
192
193#define CONFIG_CONS_INDEX 1
194#define CONFIG_SYS_NS16550
195#define CONFIG_SYS_NS16550_SERIAL
196#define CONFIG_SYS_NS16550_REG_SIZE 1
197#define CONFIG_SYS_NS16550_CLK get_serial_clock()
198
199#undef CONFIG_SYS_EXT_SERIAL_CLOCK
200#define CONFIG_SYS_BASE_BAUD 691200
201
202
203#define CONFIG_SYS_BAUDRATE_TABLE \
204 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
205 57600, 115200, 230400, 460800, 921600 }
206
207#define CONFIG_SYS_LOAD_ADDR 0x100000
208#define CONFIG_SYS_EXTBDINFO 1
209
210#define CONFIG_SYS_HZ 1000
211
212#define CONFIG_ZERO_BOOTDELAY_CHECK
213
214
215
216
217
218
219
220
221
222
223
224#define PPCHAMELON_NAND_TIMER_HACK
225
226#define CONFIG_SYS_NAND0_BASE 0xFF400000
227#define CONFIG_SYS_NAND1_BASE 0xFF000000
228#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, CONFIG_SYS_NAND1_BASE }
229#define NAND_BIG_DELAY_US 25
230#define CONFIG_SYS_MAX_NAND_DEVICE 2
231
232#define CONFIG_SYS_NAND0_CE (0x80000000 >> 1)
233#define CONFIG_SYS_NAND0_RDY (0x80000000 >> 4)
234#define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2)
235#define CONFIG_SYS_NAND0_ALE (0x80000000 >> 3)
236
237#define CONFIG_SYS_NAND1_CE (0x80000000 >> 14)
238#define CONFIG_SYS_NAND1_RDY (0x80000000 >> 31)
239#define CONFIG_SYS_NAND1_CLE (0x80000000 >> 15)
240#define CONFIG_SYS_NAND1_ALE (0x80000000 >> 16)
241
242#define MACRO_NAND_DISABLE_CE(nandptr) do \
243{ \
244 switch((unsigned long)nandptr) \
245 { \
246 case CONFIG_SYS_NAND0_BASE: \
247 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CE); \
248 break; \
249 case CONFIG_SYS_NAND1_BASE: \
250 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CE); \
251 break; \
252 } \
253} while(0)
254
255#define MACRO_NAND_ENABLE_CE(nandptr) do \
256{ \
257 switch((unsigned long)nandptr) \
258 { \
259 case CONFIG_SYS_NAND0_BASE: \
260 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CE); \
261 break; \
262 case CONFIG_SYS_NAND1_BASE: \
263 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CE); \
264 break; \
265 } \
266} while(0)
267
268#define MACRO_NAND_CTL_CLRALE(nandptr) do \
269{ \
270 switch((unsigned long)nandptr) \
271 { \
272 case CONFIG_SYS_NAND0_BASE: \
273 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_ALE); \
274 break; \
275 case CONFIG_SYS_NAND1_BASE: \
276 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_ALE); \
277 break; \
278 } \
279} while(0)
280
281#define MACRO_NAND_CTL_SETALE(nandptr) do \
282{ \
283 switch((unsigned long)nandptr) \
284 { \
285 case CONFIG_SYS_NAND0_BASE: \
286 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_ALE); \
287 break; \
288 case CONFIG_SYS_NAND1_BASE: \
289 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_ALE); \
290 break; \
291 } \
292} while(0)
293
294#define MACRO_NAND_CTL_CLRCLE(nandptr) do \
295{ \
296 switch((unsigned long)nandptr) \
297 { \
298 case CONFIG_SYS_NAND0_BASE: \
299 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CLE); \
300 break; \
301 case CONFIG_SYS_NAND1_BASE: \
302 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CLE); \
303 break; \
304 } \
305} while(0)
306
307#define MACRO_NAND_CTL_SETCLE(nandptr) do { \
308 switch((unsigned long)nandptr) { \
309 case CONFIG_SYS_NAND0_BASE: \
310 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CLE); \
311 break; \
312 case CONFIG_SYS_NAND1_BASE: \
313 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CLE); \
314 break; \
315 } \
316} while(0)
317
318
319
320
321
322#define PCI_HOST_ADAPTER 0
323#define PCI_HOST_FORCE 1
324#define PCI_HOST_AUTO 2
325
326#define CONFIG_PCI
327#define CONFIG_PCI_HOST PCI_HOST_FORCE
328#undef CONFIG_PCI_PNP
329
330
331#define CONFIG_PCI_SCAN_SHOW
332
333#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014
334#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000
335#define CONFIG_SYS_PCI_CLASSCODE 0x0b20
336
337#define CONFIG_SYS_PCI_PTM1LA 0x00000000
338#define CONFIG_SYS_PCI_PTM1MS 0xfc000001
339#define CONFIG_SYS_PCI_PTM1PCI 0x00000000
340#define CONFIG_SYS_PCI_PTM2LA 0xffc00000
341#define CONFIG_SYS_PCI_PTM2MS 0xffc00001
342#define CONFIG_SYS_PCI_PTM2PCI 0x04000000
343
344
345
346
347
348
349#define CONFIG_SYS_SDRAM_BASE 0x00000000
350
351
352
353
354
355
356
357
358
359#define CONFIG_SYS_FLASH_BASE 0xFFFB0000
360#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
361#define CONFIG_SYS_MONITOR_LEN (320 * 1024)
362
363#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
364
365
366
367
368
369
370#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
371
372
373
374#define CONFIG_SYS_MAX_FLASH_BANKS 1
375#define CONFIG_SYS_MAX_FLASH_SECT 256
376
377#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
378#define CONFIG_SYS_FLASH_WRITE_TOUT 1000
379
380#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short
381#define CONFIG_SYS_FLASH_ADDR0 0x5555
382#define CONFIG_SYS_FLASH_ADDR1 0x2AAA
383
384
385
386
387#define CONFIG_SYS_FLASH_READ0 0x0000
388#define CONFIG_SYS_FLASH_READ1 0x0001
389#define CONFIG_SYS_FLASH_READ2 0x0002
390
391#define CONFIG_SYS_FLASH_EMPTY_INFO
392
393
394
395
396#ifdef ENVIRONMENT_IN_EEPROM
397
398#define CONFIG_ENV_IS_IN_EEPROM 1
399#define CONFIG_ENV_OFFSET 0x100
400#define CONFIG_ENV_SIZE 0x700
401
402#else
403
404#define CONFIG_ENV_IS_IN_FLASH 1
405#define CONFIG_ENV_ADDR 0xFFFF8000
406#define CONFIG_ENV_SECT_SIZE 0x2000
407#define CONFIG_ENV_ADDR_REDUND 0xFFFFA000
408#define CONFIG_ENV_SIZE_REDUND 0x2000
409
410#define CONFIG_SYS_USE_PPCENV
411
412#endif
413
414
415#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500
416#define CONFIG_SYS_NVRAM_SIZE 242
417
418
419
420
421#define CONFIG_HARD_I2C
422#define CONFIG_PPC4XX_I2C
423#define CONFIG_SYS_I2C_SPEED 400000
424#define CONFIG_SYS_I2C_SLAVE 0x7F
425
426#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
427#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
428
429
430#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
431
432
433#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
434
435
436
437
438
439
440
441#define FLASH_BASE0_PRELIM 0xFFC00000
442
443
444
445
446
447
448#define CONFIG_SYS_EBC_PB0AP 0x92015480
449#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000
450
451
452
453#define CONFIG_SYS_EBC_PB1AP 0x92015480
454#define CONFIG_SYS_EBC_PB1CR 0xFF85A000
455
456
457#define CONFIG_SYS_EBC_PB2AP 0x92015480
458#define CONFIG_SYS_EBC_PB2CR 0xFF458000
459
460
461#define CONFIG_SYS_EBC_PB3AP 0x92015480
462#define CONFIG_SYS_EBC_PB3CR 0xFF058000
463
464#ifdef CONFIG_PPCHAMELEON_SMI712
465
466
467
468#define CONFIG_VIDEO
469#define CONFIG_CFB_CONSOLE
470#define CONFIG_VIDEO_SMI_LYNXEM
471#define CONFIG_VIDEO_LOGO
472
473#define CONFIG_CONSOLE_EXTRA_INFO
474#define CONFIG_VGA_AS_SINGLE_DEVICE
475
476#define CONFIG_SYS_ISA_IO 0xE8000000
477
478#define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x303
479#endif
480
481
482
483
484
485#define CONFIG_SYS_FPGA_MODE 0x00
486#define CONFIG_SYS_FPGA_STATUS 0x02
487#define CONFIG_SYS_FPGA_TS 0x04
488#define CONFIG_SYS_FPGA_TS_LOW 0x06
489#define CONFIG_SYS_FPGA_TS_CAP0 0x10
490#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12
491#define CONFIG_SYS_FPGA_TS_CAP1 0x14
492#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16
493#define CONFIG_SYS_FPGA_TS_CAP2 0x18
494#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a
495#define CONFIG_SYS_FPGA_TS_CAP3 0x1c
496#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e
497
498
499#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001
500#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
501#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000
502#define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000
503
504
505#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001
506#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002
507#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004
508#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008
509#define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000
510
511#define CONFIG_SYS_FPGA_SPARTAN2 1
512#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024
513
514
515#define CONFIG_SYS_FPGA_PRG 0x04000000
516#define CONFIG_SYS_FPGA_CLK 0x02000000
517#define CONFIG_SYS_FPGA_DATA 0x01000000
518#define CONFIG_SYS_FPGA_INIT 0x00010000
519#define CONFIG_SYS_FPGA_DONE 0x00008000
520
521
522
523
524
525#define CONFIG_SYS_TEMP_STACK_OCM 1
526
527
528#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
529#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
530#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
531#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
532
533#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
534#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549#define CONFIG_SYS_GPIO0_OSRL 0x40000550
550#define CONFIG_SYS_GPIO0_OSRH 0x00000110
551#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
552
553#define CONFIG_SYS_GPIO0_ISR1H 0x15555444
554#define CONFIG_SYS_GPIO0_TSRL 0x00000000
555#define CONFIG_SYS_GPIO0_TSRH 0x00000000
556#define CONFIG_SYS_GPIO0_TCR 0xF7FF8014
557
558#define CONFIG_NO_SERIAL_EEPROM
559
560
561
562#ifdef CONFIG_NO_SERIAL_EEPROM
563
564
565
566
567
568
569
570
571#undef AUTO_MEMORY_CONFIG
572#define DIMM_READ_ADDR 0xAB
573#define DIMM_WRITE_ADDR 0xAA
574
575
576#define PLL_ACTIVE 0x80000000
577#define CPC0_PLLMR1_SSCS 0x80000000
578#define PLL_RESET 0x40000000
579#define CPC0_PLLMR1_PLLR 0x40000000
580
581#define PLL_FBKDIV 0x00F00000
582#define CPC0_PLLMR1_FBDV 0x00F00000
583#define PLL_FBKDIV_16 0x00000000
584#define PLL_FBKDIV_1 0x00100000
585#define PLL_FBKDIV_2 0x00200000
586#define PLL_FBKDIV_3 0x00300000
587#define PLL_FBKDIV_4 0x00400000
588#define PLL_FBKDIV_5 0x00500000
589#define PLL_FBKDIV_6 0x00600000
590#define PLL_FBKDIV_7 0x00700000
591#define PLL_FBKDIV_8 0x00800000
592#define PLL_FBKDIV_9 0x00900000
593#define PLL_FBKDIV_10 0x00A00000
594#define PLL_FBKDIV_11 0x00B00000
595#define PLL_FBKDIV_12 0x00C00000
596#define PLL_FBKDIV_13 0x00D00000
597#define PLL_FBKDIV_14 0x00E00000
598#define PLL_FBKDIV_15 0x00F00000
599
600#define PLL_FWDDIVA 0x00070000
601#define CPC0_PLLMR1_FWDVA 0x00070000
602#define PLL_FWDDIVA_8 0x00000000
603#define PLL_FWDDIVA_7 0x00010000
604#define PLL_FWDDIVA_6 0x00020000
605#define PLL_FWDDIVA_5 0x00030000
606#define PLL_FWDDIVA_4 0x00040000
607#define PLL_FWDDIVA_3 0x00050000
608#define PLL_FWDDIVA_2 0x00060000
609#define PLL_FWDDIVA_1 0x00070000
610
611#define PLL_FWDDIVB 0x00007000
612#define CPC0_PLLMR1_FWDVB 0x00007000
613#define PLL_FWDDIVB_8 0x00000000
614#define PLL_FWDDIVB_7 0x00001000
615#define PLL_FWDDIVB_6 0x00002000
616#define PLL_FWDDIVB_5 0x00003000
617#define PLL_FWDDIVB_4 0x00004000
618#define PLL_FWDDIVB_3 0x00005000
619#define PLL_FWDDIVB_2 0x00006000
620#define PLL_FWDDIVB_1 0x00007000
621
622#define PLL_TUNE_MASK 0x000003FF
623#define PLL_TUNE_2_M_3 0x00000133
624#define PLL_TUNE_4_M_6 0x00000134
625#define PLL_TUNE_7_M_10 0x00000138
626#define PLL_TUNE_11_M_14 0x0000013C
627#define PLL_TUNE_15_M_40 0x0000023E
628#define PLL_TUNE_VCO_LOW 0x00000000
629#define PLL_TUNE_VCO_HI 0x00000080
630
631
632
633#define PLL_CPUDIV 0x00300000
634#define CPC0_PLLMR0_CCDV 0x00300000
635#define PLL_CPUDIV_1 0x00000000
636#define PLL_CPUDIV_2 0x00100000
637#define PLL_CPUDIV_3 0x00200000
638#define PLL_CPUDIV_4 0x00300000
639
640#define PLL_PLBDIV 0x00030000
641#define CPC0_PLLMR0_CBDV 0x00030000
642#define PLL_PLBDIV_1 0x00000000
643#define PLL_PLBDIV_2 0x00010000
644#define PLL_PLBDIV_3 0x00020000
645#define PLL_PLBDIV_4 0x00030000
646
647#define PLL_OPBDIV 0x00003000
648#define CPC0_PLLMR0_OPDV 0x00003000
649#define PLL_OPBDIV_1 0x00000000
650#define PLL_OPBDIV_2 0x00001000
651#define PLL_OPBDIV_3 0x00002000
652#define PLL_OPBDIV_4 0x00003000
653
654#define PLL_EXTBUSDIV 0x00000300
655#define CPC0_PLLMR0_EPDV 0x00000300
656#define PLL_EXTBUSDIV_2 0x00000000
657#define PLL_EXTBUSDIV_3 0x00000100
658#define PLL_EXTBUSDIV_4 0x00000200
659#define PLL_EXTBUSDIV_5 0x00000300
660
661#define PLL_MALDIV 0x00000030
662#define CPC0_PLLMR0_MPDV 0x00000030
663#define PLL_MALDIV_1 0x00000000
664#define PLL_MALDIV_2 0x00000010
665#define PLL_MALDIV_3 0x00000020
666#define PLL_MALDIV_4 0x00000030
667
668#define PLL_PCIDIV 0x00000003
669#define CPC0_PLLMR0_PPFD 0x00000003
670#define PLL_PCIDIV_1 0x00000000
671#define PLL_PCIDIV_2 0x00000001
672#define PLL_PCIDIV_3 0x00000002
673#define PLL_PCIDIV_4 0x00000003
674
675#ifdef CONFIG_PPCHAMELEON_CLK_25
676
677#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
678 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
679 PLL_MALDIV_1 | PLL_PCIDIV_4)
680#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_8 | \
681 PLL_FWDDIVA_6 | PLL_FWDDIVB_4 | \
682 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
683
684#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
685 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
686 PLL_MALDIV_1 | PLL_PCIDIV_4)
687#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8 | \
688 PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
689 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
690
691#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
692 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
693 PLL_MALDIV_1 | PLL_PCIDIV_4)
694#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
695 PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
696 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
697
698#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
699 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
700 PLL_MALDIV_1 | PLL_PCIDIV_2)
701#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
702 PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
703 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
704
705#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
706
707
708#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
709 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
710 PLL_MALDIV_1 | PLL_PCIDIV_4)
711#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_4 | \
712 PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
713 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
714
715#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
716 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
717 PLL_MALDIV_1 | PLL_PCIDIV_4)
718#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
719 PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
720 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
721
722#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
723 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
724 PLL_MALDIV_1 | PLL_PCIDIV_4)
725#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
726 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
727 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
728
729#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
730 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
731 PLL_MALDIV_1 | PLL_PCIDIV_2)
732#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
733 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
734 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
735
736#else
737#error "* External frequency (SysClk) not defined! *"
738#endif
739
740#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
741
742#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_333_111_37_55_55
743#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_333_111_37_55_55
744#define CONFIG_SYS_OPB_FREQ 55555555
745
746#elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
747#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_266_133_33_66_33
748#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_266_133_33_66_33
749#define CONFIG_SYS_OPB_FREQ 66666666
750#else
751
752#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_133_133_33_66_33
753#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_133_133_33_66_33
754#define CONFIG_SYS_OPB_FREQ 66666666
755#endif
756
757#endif
758
759#define CONFIG_JFFS2_NAND 1
760#define NAND_CACHE_PAGES 16
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766
767#undef CONFIG_CMD_MTDPARTS
768#define CONFIG_JFFS2_DEV "nand0"
769#define CONFIG_JFFS2_PART_SIZE 0x00400000
770#define CONFIG_JFFS2_PART_OFFSET 0x00000000
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792#endif
793