1/* 2 * (C) Copyright 2000, 2001 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * Modified by Udi Finkelstein udif@udif.com 6 * For the RBC823 board. 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26 27/* 28 * board/config.h - configuration options, board specific 29 */ 30 31#ifndef __CONFIG_H 32#define __CONFIG_H 33 34/* 35 * High Level Configuration Options 36 * (easy to change) 37 */ 38 39#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ 40#define CONFIG_RBC823 1 /* ...on a RBC823 module */ 41 42#define CONFIG_SYS_TEXT_BASE 0xFFF00000 43 44#if 0 45#define DEBUG 1 46#define CONFIG_LAST_STAGE_INIT 47#endif 48#define CONFIG_KEYBOARD 1 /* This board has a custom keybpard */ 49#define CONFIG_LCD 1 /* use LCD controller ... */ 50#define CONFIG_HITACHI_SP19X001_Z1A /* The LCD type we use */ 51 52#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ 53#undef CONFIG_8xx_CONS_SMC1 54#undef CONFIG_8xx_CONS_NONE 55#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ 56#if 1 57#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ 58#else 59#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 60#endif 61 62#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ 63#define CONFIG_8xx_GCLK_FREQ 48000000L 64 65#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" 66 67#undef CONFIG_BOOTARGS 68#define CONFIG_BOOTCOMMAND \ 69 "bootp; " \ 70 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ 71 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ 72 "bootm" 73 74#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 75#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 76 77#undef CONFIG_WATCHDOG /* watchdog disabled */ 78 79#define CONFIG_STATUS_LED 1 /* Status LED enabled */ 80 81#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 82 83/* 84 * BOOTP options 85 */ 86#define CONFIG_BOOTP_SUBNETMASK 87#define CONFIG_BOOTP_GATEWAY 88#define CONFIG_BOOTP_HOSTNAME 89#define CONFIG_BOOTP_BOOTPATH 90#define CONFIG_BOOTP_BOOTFILESIZE 91 92 93#undef CONFIG_MAC_PARTITION 94#define CONFIG_DOS_PARTITION 95 96#undef CONFIG_RTC_MPC8xx /* don't use internal RTC of MPC8xx (no battery) */ 97 98#define CONFIG_HARD_I2C 99#define CONFIG_SYS_I2C_SPEED 40000 100#define CONFIG_SYS_I2C_SLAVE 0xfe 101#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 102#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 103#define CONFIG_SYS_EEPROM_WRITE_BITS 4 104#define CONFIG_SYS_EEPROM_WRITE_DELAY_MS 10 105 106/* 107 * Command line configuration. 108 */ 109#include <config_cmd_default.h> 110 111#define CONFIG_CMD_ASKENV 112#define CONFIG_CMD_BEDBUG 113#define CONFIG_CMD_BMP 114#define CONFIG_CMD_CACHE 115#define CONFIG_CMD_CDP 116#define CONFIG_CMD_DHCP 117#define CONFIG_CMD_DIAG 118#define CONFIG_CMD_EEPROM 119#define CONFIG_CMD_ELF 120#define CONFIG_CMD_FAT 121#define CONFIG_CMD_I2C 122#define CONFIG_CMD_IMMAP 123#define CONFIG_CMD_KGDB 124#define CONFIG_CMD_PING 125#define CONFIG_CMD_PORTIO 126#define CONFIG_CMD_REGINFO 127#define CONFIG_CMD_SAVES 128#define CONFIG_CMD_SDRAM 129 130#undef CONFIG_CMD_SETGETDCR 131#undef CONFIG_CMD_XIMG 132 133/* 134 * Miscellaneous configurable options 135 */ 136#define CONFIG_SYS_LONGHELP /* undef to save memory */ 137#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 138#if defined(CONFIG_CMD_KGDB) 139#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 140#else 141#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 142#endif 143#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 144#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 145#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 146 147#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 148#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 149 150#define CONFIG_SYS_LOAD_ADDR 0x0100000 /* default load address */ 151 152#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 153 154/* 155 * Low Level Configuration Settings 156 * (address mappings, register initial values, etc.) 157 * You should know what you are doing if you make changes here. 158 */ 159/*----------------------------------------------------------------------- 160 * Internal Memory Mapped Register 161 */ 162#define CONFIG_SYS_IMMR 0xFF000000 163 164/*----------------------------------------------------------------------- 165 * Definitions for initial stack pointer and data area (in DPRAM) 166 */ 167#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 168#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ 169#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 170#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 171 172/*----------------------------------------------------------------------- 173 * Start addresses for the final memory configuration 174 * (Set up by the startup code) 175 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 176 */ 177#define CONFIG_SYS_SDRAM_BASE 0x00000000 178#define CONFIG_SYS_FLASH_BASE 0xFFF00000 179#if defined(DEBUG) 180#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 256 kB for Monitor */ 181#else 182#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 192 kB for Monitor */ 183#endif 184#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 185#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 186 187/* 188 * For booting Linux, the board info and command line data 189 * have to be in the first 8 MB of memory, since this is 190 * the maximum mapped by the Linux kernel during initialization. 191 */ 192#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 193 194/*----------------------------------------------------------------------- 195 * FLASH organization 196 */ 197#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 198#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ 199 200#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 201#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 202 203#define CONFIG_ENV_IS_IN_FLASH 1 204#define CONFIG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */ 205#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ 206 207/*----------------------------------------------------------------------- 208 * Cache Configuration 209 */ 210#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 211#if defined(CONFIG_CMD_KGDB) 212#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 213#endif 214 215/*----------------------------------------------------------------------- 216 * SYPCR - System Protection Control 11-9 217 * SYPCR can only be written once after reset! 218 *----------------------------------------------------------------------- 219 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 220 */ 221#if defined(CONFIG_WATCHDOG) 222#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 223 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 224#else 225/* 226#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 227*/ 228#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWRI | SYPCR_SWP) 229#endif 230 231/*----------------------------------------------------------------------- 232 * SIUMCR - SIU Module Configuration 11-6 233 *----------------------------------------------------------------------- 234 * PCMCIA config., multi-function pin tri-state 235 */ 236#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC00 | SIUMCR_FRC) 237 238/*----------------------------------------------------------------------- 239 * TBSCR - Time Base Status and Control 11-26 240 *----------------------------------------------------------------------- 241 * Clear Reference Interrupt Status, Timebase freezing enabled 242 */ 243#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 244 245/*----------------------------------------------------------------------- 246 * RTCSC - Real-Time Clock Status and Control Register 11-27 247 *----------------------------------------------------------------------- 248 */ 249#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 250 251/*----------------------------------------------------------------------- 252 * PISCR - Periodic Interrupt Status and Control 11-31 253 *----------------------------------------------------------------------- 254 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 255 */ 256#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 257 258/*----------------------------------------------------------------------- 259 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 260 *----------------------------------------------------------------------- 261 * Reset PLL lock status sticky bit, timer expired status bit and timer 262 * interrupt status bit 263 * 264 */ 265 266/* 267 * for 48 MHz, we use a 4 MHz clock * 12 268 */ 269#define CONFIG_SYS_PLPRCR \ 270 ( (12-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_LOLRE ) 271 272/*----------------------------------------------------------------------- 273 * SCCR - System Clock and reset Control Register 15-27 274 *----------------------------------------------------------------------- 275 * Set clock output, timebase and RTC source and divider, 276 * power management and some other internal clocks 277 */ 278#define SCCR_MASK SCCR_EBDF11 279#define CONFIG_SYS_SCCR (SCCR_RTDIV | SCCR_RTSEL | SCCR_CRQEN | \ 280 SCCR_PRQEN | SCCR_EBDF00 | \ 281 SCCR_COM01 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 282 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD001 | \ 283 SCCR_DFALCD00) 284 285#ifdef NOT_USED 286/*----------------------------------------------------------------------- 287 * PCMCIA stuff 288 *----------------------------------------------------------------------- 289 * 290 */ 291#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 292#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 293#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 294#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 295#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 296#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 297#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 298#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 299 300/*----------------------------------------------------------------------- 301 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 302 *----------------------------------------------------------------------- 303 */ 304 305#define CONFIG_IDE_PCCARD 1 /* Use IDE with PC Card Adapter */ 306 307#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */ 308#undef CONFIG_IDE_LED /* LED for ide not supported */ 309#undef CONFIG_IDE_RESET /* reset for ide not supported */ 310 311#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 312#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 313 314#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 315 316#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 317 318/* Offset for data I/O */ 319#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 320 321/* Offset for normal register accesses */ 322#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 323 324/* Offset for alternate registers */ 325#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 326 327#endif 328 329/*----------------------------------------------------------------------- 330 * 331 *----------------------------------------------------------------------- 332 * 333 */ 334/*#define CONFIG_SYS_DER 0x2002000F*/ 335#define CONFIG_SYS_DER 0 336 337/* 338 * Init Memory Controller: 339 * 340 * BR0/1 and OR0/1 (FLASH) 341 */ 342 343#define FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank #0 */ 344#define FLASH_BASE1_PRELIM 0x04000000 /* D.O.C Millenium */ 345 346/* used to re-map FLASH both when starting from SRAM or FLASH: 347 * restrict access enough to keep SRAM working (if any) 348 * but not too much to meddle with FLASH accesses 349 */ 350#define CONFIG_SYS_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */ 351 352/* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 7, EHTR = 1 */ 353#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_BI | OR_SCY_7_CLK | OR_EHTR) 354 355#define CONFIG_SYS_OR_TIMING_MSYS (OR_ACS_DIV1 | OR_BI) 356 357#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 358#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V) 359 360#define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_MSYS) 361#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMB | \ 362 BR_PS_8 | BR_V) 363 364/* 365 * BR4 and OR4 (SDRAM) 366 * 367 */ 368#define SDRAM_BASE4_PRELIM 0x00000000 /* SDRAM bank #0 */ 369#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ 370 371/* 372 * SDRAM timing: 373 */ 374#define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM) 375 376#define CONFIG_SYS_OR4_PRELIM (~(SDRAM_MAX_SIZE-1) | CONFIG_SYS_OR_TIMING_SDRAM ) 377#define CONFIG_SYS_BR4_PRELIM ((SDRAM_BASE4_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 378 379/* 380 * Memory Periodic Timer Prescaler 381 */ 382 383/* periodic timer for refresh */ 384#define CONFIG_SYS_MAMR_PTA 187 /* start with divider for 48 MHz */ 385 386/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ 387#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 388#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 389 390/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 391#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 392#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 393 394/* 395 * MAMR settings for SDRAM 396 */ 397 398/* 8 column SDRAM */ 399#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 400 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 401 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 402/* 9 column SDRAM */ 403#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 404 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 405 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 406 407/* 408 * JFFS2 partitions 409 * 410 */ 411/* No command line, one static partition, whole device */ 412#undef CONFIG_CMD_MTDPARTS 413#define CONFIG_JFFS2_DEV "nor0" 414#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF 415#define CONFIG_JFFS2_PART_OFFSET 0x00000000 416 417/* mtdparts command line support */ 418/* Note: fake mtd_id used, no linux mtd map file */ 419/* 420#define CONFIG_CMD_MTDPARTS 421#define MTDIDS_DEFAULT "" 422#define MTDPARTS_DEFAULT "" 423*/ 424 425#endif /* __CONFIG_H */ 426