1/* 2 * (C) Copyright 2001 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* 25 * board/config.h - configuration options, board specific 26 */ 27 28#ifndef __CONFIG_H 29#define __CONFIG_H 30 31/* 32 * High Level Configuration Options 33 * (easy to change) 34 */ 35 36#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ 37#define CONFIG_TQM8260 200 /* ...on a TQM8260 module Rev.200 */ 38#define CONFIG_SCM 1 /* ...on a System Controller Module */ 39#define CONFIG_CPM2 1 /* Has a CPM2 */ 40 41#define CONFIG_SYS_TEXT_BASE 0x40000000 42 43#if (CONFIG_TQM8260 <= 100) 44# error "TQM8260 module revison not supported" 45#endif 46 47/* We use a TQM8260 module with a 300MHz CPU */ 48#define CONFIG_300MHz 49 50/* Define 60x busmode only if your TQM8260 has L2 cache! */ 51#ifdef CONFIG_L2_CACHE 52# define CONFIG_BUSMODE_60x 1 /* bus mode: 60x */ 53#else 54# undef CONFIG_BUSMODE_60x /* bus mode: 8260 */ 55#endif 56 57/* The board with 300MHz CPU doesn't have L2 cache, but works in 60x bus mode */ 58#ifdef CONFIG_300MHz 59# define CONFIG_BUSMODE_60x 60#endif 61 62#define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */ 63 64#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 65 66#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ 67 68#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" 69 70#undef CONFIG_BOOTARGS 71#define CONFIG_BOOTCOMMAND \ 72 "bootp; " \ 73 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ 74 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ 75 "bootm" 76 77/* enable I2C and select the hardware/software driver */ 78#undef CONFIG_HARD_I2C /* I2C with hardware support */ 79#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ 80#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 81#define CONFIG_SYS_I2C_SLAVE 0x7F 82 83/* 84 * Software (bit-bang) I2C driver configuration 85 */ 86 87#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ 88#define I2C_ACTIVE (iop->pdir |= 0x00010000) 89#define I2C_TRISTATE (iop->pdir &= ~0x00010000) 90#define I2C_READ ((iop->pdat & 0x00010000) != 0) 91#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ 92 else iop->pdat &= ~0x00010000 93#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ 94 else iop->pdat &= ~0x00020000 95#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ 96 97#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 98#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 99#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 100#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ 101 102#define CONFIG_I2C_X 103 104/* 105 * select serial console configuration 106 * 107 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then 108 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 109 * for SCC). 110 * 111 * if CONFIG_CONS_NONE is defined, then the serial console routines must 112 * defined elsewhere (for example, on the cogent platform, there are serial 113 * ports on the motherboard which are used for the serial console - see 114 * cogent/cma101/serial.[ch]). 115 */ 116#define CONFIG_CONS_ON_SMC /* define if console on SMC */ 117#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ 118#undef CONFIG_CONS_NONE /* define if console on something else*/ 119#ifdef CONFIG_82xx_CONS_SMC1 120#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ 121#endif 122#ifdef CONFIG_82xx_CONS_SMC2 123#define CONFIG_CONS_INDEX 2 /* which serial channel for console */ 124#endif 125 126#undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ 127#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */ 128#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9 */ 129 130/* 131 * select ethernet configuration 132 * 133 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then 134 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 135 * for FCC) 136 * 137 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be 138 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. 139 * 140 * (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the 141 * X.29 connector, and FCC2 is hardwired to the X.1 connector) 142 */ 143#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ 144#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ 145#undef CONFIG_ETHER_NONE /* define if ether on something else */ 146#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ 147 148#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1) 149 150/* 151 * - Rx-CLK is CLK12 152 * - Tx-CLK is CLK11 153 * - RAM for BD/Buffers is on the 60x Bus (see 28-13) 154 * - Enable Full Duplex in FSMR 155 */ 156# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) 157# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK12|CMXFCR_TF1CS_CLK11) 158# define CONFIG_SYS_CPMFCR_RAMTYPE 0 159# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) 160 161#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3) 162 163/* 164 * - Rx-CLK is CLK15 165 * - Tx-CLK is CLK16 166 * - RAM for BD/Buffers is on the 60x Bus (see 28-13) 167 * - Enable Full Duplex in FSMR 168 */ 169# define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) 170# define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) 171# define CONFIG_SYS_CPMFCR_RAMTYPE 0 172# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) 173 174#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ 175 176 177/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ 178#ifndef CONFIG_300MHz 179#define CONFIG_8260_CLKIN 66666666 /* in Hz */ 180#else 181#define CONFIG_8260_CLKIN 83333000 /* in Hz */ 182#endif 183 184#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) 185#define CONFIG_BAUDRATE 230400 186#else 187#define CONFIG_BAUDRATE 115200 188#endif 189 190#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 191#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 192 193#undef CONFIG_WATCHDOG /* watchdog disabled */ 194 195/* 196 * BOOTP options 197 */ 198#define CONFIG_BOOTP_SUBNETMASK 199#define CONFIG_BOOTP_GATEWAY 200#define CONFIG_BOOTP_HOSTNAME 201#define CONFIG_BOOTP_BOOTPATH 202#define CONFIG_BOOTP_BOOTFILESIZE 203 204 205/* 206 * Command line configuration. 207 */ 208#include <config_cmd_default.h> 209 210#define CONFIG_CMD_DHCP 211#define CONFIG_CMD_I2C 212#define CONFIG_CMD_EEPROM 213#define CONFIG_CMD_BSP 214 215 216/* 217 * Miscellaneous configurable options 218 */ 219#define CONFIG_SYS_LONGHELP /* undef to save memory */ 220#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 221#if defined(CONFIG_CMD_KGDB) 222#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 223#else 224#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 225#endif 226#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 227#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 228#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 229 230#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 231#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 232 233#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 234 235#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 236 237#define CONFIG_SYS_RESET_ADDRESS 0xFFFFFFFC /* "bad" address */ 238 239#define CONFIG_MISC_INIT_R /* have misc_init_r() function */ 240 241/* 242 * For booting Linux, the board info and command line data 243 * have to be in the first 8 MB of memory, since this is 244 * the maximum mapped by the Linux kernel during initialization. 245 */ 246#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 247 248 249/* What should the base address of the main FLASH be and how big is 250 * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/tqm8260/config.mk 251 * The main FLASH is whichever is connected to *CS0. 252 */ 253#define CONFIG_SYS_FLASH0_BASE 0x40000000 254#define CONFIG_SYS_FLASH1_BASE 0x60000000 255#define CONFIG_SYS_FLASH0_SIZE 32 256#define CONFIG_SYS_FLASH1_SIZE 32 257 258/* Flash bank size (for preliminary settings) 259 */ 260#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE 261 262/*----------------------------------------------------------------------- 263 * FLASH organization 264 */ 265#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ 266#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ 267 268#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ 269#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ 270 271#if 0 272/* Start port with environment in flash; switch to EEPROM later */ 273#define CONFIG_ENV_IS_IN_FLASH 1 274#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x40000) 275#define CONFIG_ENV_SIZE 0x40000 276#define CONFIG_ENV_SECT_SIZE 0x40000 277#else 278/* Final version: environment in EEPROM */ 279#define CONFIG_ENV_IS_IN_EEPROM 1 280#define CONFIG_ENV_OFFSET 0 281#define CONFIG_ENV_SIZE 2048 282#endif 283 284/*----------------------------------------------------------------------- 285 * Hardware Information Block 286 */ 287#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 288#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 289#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 290 291/*----------------------------------------------------------------------- 292 * Hard Reset Configuration Words 293 * 294 * if you change bits in the HRCW, you must also change the CONFIG_SYS_* 295 * defines for the various registers affected by the HRCW e.g. changing 296 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. 297 */ 298#if defined(CONFIG_266MHz) 299#define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \ 300 HRCW_MODCK_H0111) 301#elif defined(CONFIG_300MHz) 302#define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \ 303 HRCW_MODCK_H0110) 304#else 305#define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS) 306#endif 307 308/* no slaves so just fill with zeros */ 309#define CONFIG_SYS_HRCW_SLAVE1 0 310#define CONFIG_SYS_HRCW_SLAVE2 0 311#define CONFIG_SYS_HRCW_SLAVE3 0 312#define CONFIG_SYS_HRCW_SLAVE4 0 313#define CONFIG_SYS_HRCW_SLAVE5 0 314#define CONFIG_SYS_HRCW_SLAVE6 0 315#define CONFIG_SYS_HRCW_SLAVE7 0 316 317/*----------------------------------------------------------------------- 318 * Internal Memory Mapped Register 319 */ 320#define CONFIG_SYS_IMMR 0xFFF00000 321 322/*----------------------------------------------------------------------- 323 * Definitions for initial stack pointer and data area (in DPRAM) 324 */ 325#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 326#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ 327#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 328#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 329 330/*----------------------------------------------------------------------- 331 * Start addresses for the final memory configuration 332 * (Set up by the startup code) 333 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 334 * 335 * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM 336 * is mapped at SDRAM_BASE2_PRELIM. 337 */ 338#define CONFIG_SYS_SDRAM_BASE 0x00000000 339#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE 340#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 341#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 342#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ 343 344/*----------------------------------------------------------------------- 345 * Hardware Information Block 346 */ 347#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 348#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 349#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 350 351/*----------------------------------------------------------------------- 352 * Cache Configuration 353 */ 354#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ 355#if defined(CONFIG_CMD_KGDB) 356# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 357#endif 358 359/*----------------------------------------------------------------------- 360 * HIDx - Hardware Implementation-dependent Registers 2-11 361 *----------------------------------------------------------------------- 362 * HID0 also contains cache control - initially enable both caches and 363 * invalidate contents, then the final state leaves only the instruction 364 * cache enabled. Note that Power-On and Hard reset invalidate the caches, 365 * but Soft reset does not. 366 * 367 * HID1 has only read-only information - nothing to set. 368 */ 369#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ 370 HID0_IFEM|HID0_ABE) 371#define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE) 372#define CONFIG_SYS_HID2 0 373 374/*----------------------------------------------------------------------- 375 * RMR - Reset Mode Register 5-5 376 *----------------------------------------------------------------------- 377 * turn on Checkstop Reset Enable 378 */ 379#define CONFIG_SYS_RMR RMR_CSRE 380 381/*----------------------------------------------------------------------- 382 * BCR - Bus Configuration 4-25 383 *----------------------------------------------------------------------- 384 */ 385#ifdef CONFIG_BUSMODE_60x 386#define CONFIG_SYS_BCR (BCR_EBM|BCR_L2C|BCR_LETM|\ 387 BCR_NPQM0|BCR_NPQM1|BCR_NPQM2) /* 60x mode */ 388#else 389#define BCR_APD01 0x10000000 390#define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ 391#endif 392 393/*----------------------------------------------------------------------- 394 * SIUMCR - SIU Module Configuration 4-31 395 *----------------------------------------------------------------------- 396 */ 397#if 0 398#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10) 399#else 400#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10) 401#endif 402 403 404/*----------------------------------------------------------------------- 405 * SYPCR - System Protection Control 4-35 406 * SYPCR can only be written once after reset! 407 *----------------------------------------------------------------------- 408 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable 409 */ 410#if defined(CONFIG_WATCHDOG) 411#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ 412 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) 413#else 414#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ 415 SYPCR_SWRI|SYPCR_SWP) 416#endif /* CONFIG_WATCHDOG */ 417 418/*----------------------------------------------------------------------- 419 * TMCNTSC - Time Counter Status and Control 4-40 420 *----------------------------------------------------------------------- 421 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, 422 * and enable Time Counter 423 */ 424#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) 425 426/*----------------------------------------------------------------------- 427 * PISCR - Periodic Interrupt Status and Control 4-42 428 *----------------------------------------------------------------------- 429 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable 430 * Periodic timer 431 */ 432#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) 433 434/*----------------------------------------------------------------------- 435 * SCCR - System Clock Control 9-8 436 *----------------------------------------------------------------------- 437 * Ensure DFBRG is Divide by 16 438 */ 439#define CONFIG_SYS_SCCR 0 440 441/*----------------------------------------------------------------------- 442 * RCCR - RISC Controller Configuration 13-7 443 *----------------------------------------------------------------------- 444 */ 445#define CONFIG_SYS_RCCR 0 446 447/* 448 * Init Memory Controller: 449 * 450 * Bank Bus Machine PortSz Device 451 * ---- --- ------- ------ ------ 452 * 0 60x GPCM 64 bit FLASH 453 * 1 60x SDRAM 64 bit SDRAM 454 * 2 Local SDRAM 32 bit SDRAM 455 * 456 */ 457 458 /* Initialize SDRAM on local bus 459 */ 460#define CONFIG_SYS_INIT_LOCAL_SDRAM 461 462#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ 463 464/* Minimum mask to separate preliminary 465 * address ranges for CS[0:2] 466 */ 467#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */ 468#define CONFIG_SYS_LOCAL_SDRAM_LIMIT (128<<20) /* less than 128 MB */ 469 470#define CONFIG_SYS_MPTPR 0x4000 471 472/*----------------------------------------------------------------------------- 473 * Address for Mode Register Set (MRS) command 474 *----------------------------------------------------------------------------- 475 * In fact, the address is rather configuration data presented to the SDRAM on 476 * its address lines. Because the address lines may be mux'ed externally either 477 * for 8 column or 9 column devices, some bits appear twice in the 8260's 478 * address: 479 * 480 * | (RFU) | (RFU) | WBL | TM | CL | BT | Burst Length | 481 * | BA1 BA0 | A12 : A10 | A9 | A8 A7 | A6 : A4 | A3 | A2 : A0 | 482 * 8 columns mux'ing: | A9 | A10 A21 | A22 : A24 | A25 | A26 : A28 | 483 * 9 columns mux'ing: | A8 | A20 A21 | A22 : A24 | A25 | A26 : A28 | 484 * Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 | 485 *----------------------------------------------------------------------------- 486 */ 487#define CONFIG_SYS_MRS_OFFS 0x00000110 488 489 490/* Bank 0 - FLASH 491 */ 492#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ 493 BRx_PS_64 |\ 494 BRx_MS_GPCM_P |\ 495 BRx_V) 496 497#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ 498 ORxG_CSNT |\ 499 ORxG_ACS_DIV1 |\ 500 ORxG_SCY_3_CLK |\ 501 ORxG_EHTR |\ 502 ORxG_TRLX) 503 504 /* SDRAM on TQM8260 can have either 8 or 9 columns. 505 * The number affects configuration values. 506 */ 507 508/* Bank 1 - 60x bus SDRAM 509 */ 510#define CONFIG_SYS_PSRT 0x20 511#define CONFIG_SYS_LSRT 0x20 512#ifndef CONFIG_SYS_RAMBOOT 513#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ 514 BRx_PS_64 |\ 515 BRx_MS_SDRAM_P |\ 516 BRx_V) 517 518#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1_8COL 519 520 521 /* SDRAM initialization values for 8-column chips 522 */ 523#define CONFIG_SYS_OR1_8COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ 524 ORxS_BPD_4 |\ 525 ORxS_ROWST_PBI1_A7 |\ 526 ORxS_NUMR_12) 527 528#define CONFIG_SYS_PSDMR_8COL (PSDMR_PBI |\ 529 PSDMR_SDAM_A15_IS_A5 |\ 530 PSDMR_BSMA_A12_A14 |\ 531 PSDMR_SDA10_PBI1_A8 |\ 532 PSDMR_RFRC_7_CLK |\ 533 PSDMR_PRETOACT_2W |\ 534 PSDMR_ACTTORW_2W |\ 535 PSDMR_LDOTOPRE_1C |\ 536 PSDMR_WRC_2C |\ 537 PSDMR_EAMUX |\ 538 PSDMR_CL_2) 539 540 /* SDRAM initialization values for 9-column chips 541 */ 542#define CONFIG_SYS_OR1_9COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ 543 ORxS_BPD_4 |\ 544 ORxS_ROWST_PBI1_A5 |\ 545 ORxS_NUMR_13) 546 547#define CONFIG_SYS_PSDMR_9COL (PSDMR_PBI |\ 548 PSDMR_SDAM_A16_IS_A5 |\ 549 PSDMR_BSMA_A12_A14 |\ 550 PSDMR_SDA10_PBI1_A7 |\ 551 PSDMR_RFRC_7_CLK |\ 552 PSDMR_PRETOACT_2W |\ 553 PSDMR_ACTTORW_2W |\ 554 PSDMR_LDOTOPRE_1C |\ 555 PSDMR_WRC_2C |\ 556 PSDMR_EAMUX |\ 557 PSDMR_CL_2) 558 559/* Bank 2 - Local bus SDRAM 560 */ 561#ifdef CONFIG_SYS_INIT_LOCAL_SDRAM 562#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\ 563 BRx_PS_32 |\ 564 BRx_MS_SDRAM_L |\ 565 BRx_V) 566 567#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_8COL 568 569#define SDRAM_BASE2_PRELIM 0x80000000 570 571 /* SDRAM initialization values for 8-column chips 572 */ 573#define CONFIG_SYS_OR2_8COL ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ 574 ORxS_BPD_4 |\ 575 ORxS_ROWST_PBI1_A8 |\ 576 ORxS_NUMR_12) 577 578#define CONFIG_SYS_LSDMR_8COL (PSDMR_PBI |\ 579 PSDMR_SDAM_A15_IS_A5 |\ 580 PSDMR_BSMA_A13_A15 |\ 581 PSDMR_SDA10_PBI1_A9 |\ 582 PSDMR_RFRC_7_CLK |\ 583 PSDMR_PRETOACT_2W |\ 584 PSDMR_ACTTORW_2W |\ 585 PSDMR_BL |\ 586 PSDMR_LDOTOPRE_1C |\ 587 PSDMR_WRC_2C |\ 588 PSDMR_CL_2) 589 590 /* SDRAM initialization values for 9-column chips 591 */ 592#define CONFIG_SYS_OR2_9COL ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ 593 ORxS_BPD_4 |\ 594 ORxS_ROWST_PBI1_A6 |\ 595 ORxS_NUMR_13) 596 597#define CONFIG_SYS_LSDMR_9COL (PSDMR_PBI |\ 598 PSDMR_SDAM_A16_IS_A5 |\ 599 PSDMR_BSMA_A13_A15 |\ 600 PSDMR_SDA10_PBI1_A8 |\ 601 PSDMR_RFRC_7_CLK |\ 602 PSDMR_PRETOACT_2W |\ 603 PSDMR_ACTTORW_2W |\ 604 PSDMR_BL |\ 605 PSDMR_LDOTOPRE_1C |\ 606 PSDMR_WRC_2C |\ 607 PSDMR_CL_2) 608 609#endif /* CONFIG_SYS_INIT_LOCAL_SDRAM */ 610 611#endif /* CONFIG_SYS_RAMBOOT */ 612 613#define CONFIG_SYS_CAN0_BASE 0xc0000000 614#define CONFIG_SYS_CAN1_BASE 0xc0008000 615#define CONFIG_SYS_FIOX_BASE 0xc0010000 616#define CONFIG_SYS_FDOHM_BASE 0xc0018000 617#define CONFIG_SYS_EXTPROM_BASE 0xc2000000 618 619#define CONFIG_SYS_CAN_SIZE 0x00000100 620#define CONFIG_SYS_FIOX_SIZE 0x00000020 621#define CONFIG_SYS_FDOHM_SIZE 0x00002000 622#define CONFIG_SYS_EXTPROM_BANK_SIZE 0x01000000 623 624#define EXT_EEPROM_MAX_FLASH_BANKS 0x02 625 626/* CS3 - CAN 0 627 */ 628#define CONFIG_SYS_CAN0_BR3 ((CONFIG_SYS_CAN0_BASE & BRx_BA_MSK) |\ 629 BRx_PS_8 |\ 630 BRx_MS_UPMA |\ 631 BRx_V) 632 633#define CONFIG_SYS_CAN0_OR3 (P2SZ_TO_AM(CONFIG_SYS_CAN_SIZE) |\ 634 ORxU_BI |\ 635 ORxU_EHTR_4IDLE) 636 637/* CS4 - CAN 1 638 */ 639#define CONFIG_SYS_CAN1_BR4 ((CONFIG_SYS_CAN1_BASE & BRx_BA_MSK) |\ 640 BRx_PS_8 |\ 641 BRx_MS_UPMA |\ 642 BRx_V) 643 644#define CONFIG_SYS_CAN1_OR4 (P2SZ_TO_AM(CONFIG_SYS_CAN_SIZE) |\ 645 ORxU_BI |\ 646 ORxU_EHTR_4IDLE) 647 648/* CS5 - Extended PROM (16MB optional) 649 */ 650#define CONFIG_SYS_EXTPROM_BR5 ((CONFIG_SYS_EXTPROM_BASE & BRx_BA_MSK)|\ 651 BRx_PS_32 |\ 652 BRx_MS_GPCM_P |\ 653 BRx_V) 654 655#define CONFIG_SYS_EXTPROM_OR5 (P2SZ_TO_AM(CONFIG_SYS_EXTPROM_BANK_SIZE)|\ 656 ORxG_CSNT |\ 657 ORxG_ACS_DIV4 |\ 658 ORxG_SCY_5_CLK |\ 659 ORxG_TRLX) 660 661/* CS6 - Extended PROM (16MB optional) 662 */ 663#define CONFIG_SYS_EXTPROM_BR6 (((CONFIG_SYS_EXTPROM_BASE + \ 664 CONFIG_SYS_EXTPROM_BANK_SIZE) & BRx_BA_MSK)|\ 665 BRx_PS_32 |\ 666 BRx_MS_GPCM_P |\ 667 BRx_V) 668 669#define CONFIG_SYS_EXTPROM_OR6 (P2SZ_TO_AM(CONFIG_SYS_EXTPROM_BANK_SIZE)|\ 670 ORxG_CSNT |\ 671 ORxG_ACS_DIV4 |\ 672 ORxG_SCY_5_CLK |\ 673 ORxG_TRLX) 674 675/* CS7 - FPGA FIOX: Glue Logic 676 */ 677#define CONFIG_SYS_FIOX_BR7 ((CONFIG_SYS_FIOX_BASE & BRx_BA_MSK) |\ 678 BRx_PS_32 |\ 679 BRx_MS_GPCM_P |\ 680 BRx_V) 681 682#define CONFIG_SYS_FIOX_OR7 (P2SZ_TO_AM(CONFIG_SYS_FIOX_SIZE) |\ 683 ORxG_ACS_DIV4 |\ 684 ORxG_SCY_5_CLK |\ 685 ORxG_TRLX) 686 687/* CS8 - FPGA DOH Master 688 */ 689#define CONFIG_SYS_FDOHM_BR8 ((CONFIG_SYS_FDOHM_BASE & BRx_BA_MSK) |\ 690 BRx_PS_16 |\ 691 BRx_MS_GPCM_P |\ 692 BRx_V) 693 694#define CONFIG_SYS_FDOHM_OR8 (P2SZ_TO_AM(CONFIG_SYS_FDOHM_SIZE) |\ 695 ORxG_ACS_DIV4 |\ 696 ORxG_SCY_5_CLK |\ 697 ORxG_TRLX) 698 699 700/* FPGA configuration */ 701#define CONFIG_SYS_PD_FIOX_PROG (1 << (31- 5)) /* PD 5 */ 702#define CONFIG_SYS_PD_FIOX_DONE (1 << (31-28)) /* PD 28 */ 703#define CONFIG_SYS_PD_FIOX_INIT (1 << (31-29)) /* PD 29 */ 704 705#define CONFIG_SYS_PD_FDOHM_PROG (1 << (31- 4)) /* PD 4 */ 706#define CONFIG_SYS_PD_FDOHM_DONE (1 << (31-26)) /* PD 26 */ 707#define CONFIG_SYS_PD_FDOHM_INIT (1 << (31-27)) /* PD 27 */ 708 709 710#endif /* __CONFIG_H */ 711