1/* 2 * (C) Copyright 2000-2008 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* 25 * board/config.h - configuration options, board specific 26 */ 27 28#ifndef __CONFIG_H 29#define __CONFIG_H 30 31/* 32 * High Level Configuration Options 33 * (easy to change) 34 */ 35 36#define CONFIG_MPC855 1 /* This is a MPC855 CPU */ 37#define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */ 38 39#define CONFIG_SYS_TEXT_BASE 0x40000000 40 41#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 42#define CONFIG_SYS_SMC_RXBUFLEN 128 43#define CONFIG_SYS_MAXIDLE 10 44#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ 45 46#define CONFIG_BOOTCOUNT_LIMIT 47 48#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 49 50#define CONFIG_BOARD_TYPES 1 /* support board types */ 51 52#define CONFIG_PREBOOT "echo;" \ 53 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 54 "echo" 55 56#undef CONFIG_BOOTARGS 57 58#define CONFIG_EXTRA_ENV_SETTINGS \ 59 "netdev=eth0\0" \ 60 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 61 "nfsroot=${serverip}:${rootpath}\0" \ 62 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 63 "addip=setenv bootargs ${bootargs} " \ 64 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 65 ":${hostname}:${netdev}:off panic=1\0" \ 66 "flash_nfs=run nfsargs addip;" \ 67 "bootm ${kernel_addr}\0" \ 68 "flash_self=run ramargs addip;" \ 69 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 70 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 71 "rootpath=/opt/eldk/ppc_8xx\0" \ 72 "hostname=TQM855M\0" \ 73 "bootfile=TQM855M/uImage\0" \ 74 "fdt_addr=40080000\0" \ 75 "kernel_addr=400A0000\0" \ 76 "ramdisk_addr=40280000\0" \ 77 "u-boot=TQM855M/u-image.bin\0" \ 78 "load=tftp 200000 ${u-boot}\0" \ 79 "update=prot off 40000000 +${filesize};" \ 80 "era 40000000 +${filesize};" \ 81 "cp.b 200000 40000000 ${filesize};" \ 82 "sete filesize;save\0" \ 83 "" 84#define CONFIG_BOOTCOMMAND "run flash_self" 85 86#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 87#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 88 89#undef CONFIG_WATCHDOG /* watchdog disabled */ 90 91#define CONFIG_STATUS_LED 1 /* Status LED enabled */ 92 93#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 94 95/* enable I2C and select the hardware/software driver */ 96#undef CONFIG_HARD_I2C /* I2C with hardware support */ 97#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ 98 99#define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */ 100#define CONFIG_SYS_I2C_SLAVE 0xFE 101 102#ifdef CONFIG_SOFT_I2C 103/* 104 * Software (bit-bang) I2C driver configuration 105 */ 106#define PB_SCL 0x00000020 /* PB 26 */ 107#define PB_SDA 0x00000010 /* PB 27 */ 108 109#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) 110#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) 111#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) 112#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) 113#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ 114 else immr->im_cpm.cp_pbdat &= ~PB_SDA 115#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ 116 else immr->im_cpm.cp_pbdat &= ~PB_SCL 117#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ 118#endif /* CONFIG_SOFT_I2C */ 119 120#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */ 121#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ 122#if 0 123#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */ 124#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01 125#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 126#endif 127 128/* 129 * BOOTP options 130 */ 131#define CONFIG_BOOTP_SUBNETMASK 132#define CONFIG_BOOTP_GATEWAY 133#define CONFIG_BOOTP_HOSTNAME 134#define CONFIG_BOOTP_BOOTPATH 135#define CONFIG_BOOTP_BOOTFILESIZE 136 137 138#define CONFIG_MAC_PARTITION 139#define CONFIG_DOS_PARTITION 140 141#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 142 143 144/* 145 * Command line configuration. 146 */ 147#include <config_cmd_default.h> 148 149#define CONFIG_CMD_ASKENV 150#define CONFIG_CMD_DATE 151#define CONFIG_CMD_DHCP 152#define CONFIG_CMD_ELF 153#define CONFIG_CMD_EXT2 154#define CONFIG_CMD_EEPROM 155#define CONFIG_CMD_IDE 156#define CONFIG_CMD_JFFS2 157#define CONFIG_CMD_NFS 158#define CONFIG_CMD_SNTP 159 160 161#define CONFIG_NETCONSOLE 162 163 164/* 165 * Miscellaneous configurable options 166 */ 167#define CONFIG_SYS_LONGHELP /* undef to save memory */ 168#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 169 170#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 171#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ 172 173#if defined(CONFIG_CMD_KGDB) 174#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 175#else 176#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 177#endif 178#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 179#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 180#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 181 182#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 183#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 184 185#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 186 187#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 188 189/* 190 * Low Level Configuration Settings 191 * (address mappings, register initial values, etc.) 192 * You should know what you are doing if you make changes here. 193 */ 194/*----------------------------------------------------------------------- 195 * Internal Memory Mapped Register 196 */ 197#define CONFIG_SYS_IMMR 0xFFF00000 198 199/*----------------------------------------------------------------------- 200 * Definitions for initial stack pointer and data area (in DPRAM) 201 */ 202#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 203#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ 204#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 205#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 206 207/*----------------------------------------------------------------------- 208 * Start addresses for the final memory configuration 209 * (Set up by the startup code) 210 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 211 */ 212#define CONFIG_SYS_SDRAM_BASE 0x00000000 213#define CONFIG_SYS_FLASH_BASE 0x40000000 214#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 215#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 216#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 217 218/* 219 * For booting Linux, the board info and command line data 220 * have to be in the first 8 MB of memory, since this is 221 * the maximum mapped by the Linux kernel during initialization. 222 */ 223#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 224 225/*----------------------------------------------------------------------- 226 * FLASH organization 227 */ 228 229/* use CFI flash driver */ 230#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 231#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 232#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 233#define CONFIG_SYS_FLASH_EMPTY_INFO 234#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 235#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 236#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 237 238#define CONFIG_ENV_IS_IN_FLASH 1 239#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ 240#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ 241#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ 242 243/* Address and size of Redundant Environment Sector */ 244#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) 245#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 246 247#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ 248 249#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ 250 251/*----------------------------------------------------------------------- 252 * Dynamic MTD partition support 253 */ 254#define CONFIG_CMD_MTDPARTS 255#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 256#define CONFIG_FLASH_CFI_MTD 257#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" 258 259#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ 260 "128k(dtb)," \ 261 "1920k(kernel)," \ 262 "5632(rootfs)," \ 263 "4m(data)" 264 265/*----------------------------------------------------------------------- 266 * Hardware Information Block 267 */ 268#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 269#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 270#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 271 272/*----------------------------------------------------------------------- 273 * Cache Configuration 274 */ 275#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 276#if defined(CONFIG_CMD_KGDB) 277#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 278#endif 279 280/*----------------------------------------------------------------------- 281 * SYPCR - System Protection Control 11-9 282 * SYPCR can only be written once after reset! 283 *----------------------------------------------------------------------- 284 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 285 */ 286#if defined(CONFIG_WATCHDOG) 287#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 288 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 289#else 290#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 291#endif 292 293/*----------------------------------------------------------------------- 294 * SIUMCR - SIU Module Configuration 11-6 295 *----------------------------------------------------------------------- 296 * PCMCIA config., multi-function pin tri-state 297 */ 298#ifndef CONFIG_CAN_DRIVER 299#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 300#else /* we must activate GPL5 in the SIUMCR for CAN */ 301#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 302#endif /* CONFIG_CAN_DRIVER */ 303 304/*----------------------------------------------------------------------- 305 * TBSCR - Time Base Status and Control 11-26 306 *----------------------------------------------------------------------- 307 * Clear Reference Interrupt Status, Timebase freezing enabled 308 */ 309#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 310 311/*----------------------------------------------------------------------- 312 * RTCSC - Real-Time Clock Status and Control Register 11-27 313 *----------------------------------------------------------------------- 314 */ 315#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 316 317/*----------------------------------------------------------------------- 318 * PISCR - Periodic Interrupt Status and Control 11-31 319 *----------------------------------------------------------------------- 320 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 321 */ 322#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 323 324/*----------------------------------------------------------------------- 325 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 326 *----------------------------------------------------------------------- 327 * Reset PLL lock status sticky bit, timer expired status bit and timer 328 * interrupt status bit 329 */ 330#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 331 332/*----------------------------------------------------------------------- 333 * SCCR - System Clock and reset Control Register 15-27 334 *----------------------------------------------------------------------- 335 * Set clock output, timebase and RTC source and divider, 336 * power management and some other internal clocks 337 */ 338#define SCCR_MASK SCCR_EBDF11 339#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 340 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 341 SCCR_DFALCD00) 342 343/*----------------------------------------------------------------------- 344 * PCMCIA stuff 345 *----------------------------------------------------------------------- 346 * 347 */ 348#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 349#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 350#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 351#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 352#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 353#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 354#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 355#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 356 357/*----------------------------------------------------------------------- 358 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 359 *----------------------------------------------------------------------- 360 */ 361 362#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 363 364#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 365#undef CONFIG_IDE_LED /* LED for ide not supported */ 366#undef CONFIG_IDE_RESET /* reset for ide not supported */ 367 368#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 369#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 370 371#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 372 373#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 374 375/* Offset for data I/O */ 376#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 377 378/* Offset for normal register accesses */ 379#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 380 381/* Offset for alternate registers */ 382#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 383 384/*----------------------------------------------------------------------- 385 * 386 *----------------------------------------------------------------------- 387 * 388 */ 389#define CONFIG_SYS_DER 0 390 391/* 392 * Init Memory Controller: 393 * 394 * BR0/1 and OR0/1 (FLASH) 395 */ 396 397#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 398#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ 399 400/* used to re-map FLASH both when starting from SRAM or FLASH: 401 * restrict access enough to keep SRAM working (if any) 402 * but not too much to meddle with FLASH accesses 403 */ 404#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 405#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 406 407/* 408 * FLASH timing: 409 */ 410#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ 411 OR_SCY_3_CLK | OR_EHTR | OR_BI) 412 413#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 414#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 415#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 416 417#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 418#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 419#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) 420 421/* 422 * BR2/3 and OR2/3 (SDRAM) 423 * 424 */ 425#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ 426#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ 427#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ 428 429/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 430#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 431 432#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 433#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 434 435#ifndef CONFIG_CAN_DRIVER 436#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 437#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 438#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ 439#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ 440#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ 441#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) 442#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ 443 BR_PS_8 | BR_MS_UPMB | BR_V ) 444#endif /* CONFIG_CAN_DRIVER */ 445 446/* 447 * Memory Periodic Timer Prescaler 448 * 449 * The Divider for PTA (refresh timer) configuration is based on an 450 * example SDRAM configuration (64 MBit, one bank). The adjustment to 451 * the number of chip selects (NCS) and the actually needed refresh 452 * rate is done by setting MPTPR. 453 * 454 * PTA is calculated from 455 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) 456 * 457 * gclk CPU clock (not bus clock!) 458 * Trefresh Refresh cycle * 4 (four word bursts used) 459 * 460 * 4096 Rows from SDRAM example configuration 461 * 1000 factor s -> ms 462 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration 463 * 4 Number of refresh cycles per period 464 * 64 Refresh cycle in ms per number of rows 465 * -------------------------------------------- 466 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 467 * 468 * 50 MHz => 50.000.000 / Divider = 98 469 * 66 Mhz => 66.000.000 / Divider = 129 470 * 80 Mhz => 80.000.000 / Divider = 156 471 */ 472 473#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) 474#define CONFIG_SYS_MAMR_PTA 98 475 476/* 477 * For 16 MBit, refresh rates could be 31.3 us 478 * (= 64 ms / 2K = 125 / quad bursts). 479 * For a simpler initialization, 15.6 us is used instead. 480 * 481 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks 482 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank 483 */ 484#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 485#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 486 487/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 488#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 489#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 490 491/* 492 * MAMR settings for SDRAM 493 */ 494 495/* 8 column SDRAM */ 496#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 497 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 498 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 499/* 9 column SDRAM */ 500#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 501 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 502 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 503 504#define CONFIG_SCC1_ENET 505#define CONFIG_FEC_ENET 506#define CONFIG_ETHPRIME "SCC" 507 508/* pass open firmware flat tree */ 509#define CONFIG_OF_LIBFDT 1 510#define CONFIG_OF_BOARD_SETUP 1 511#define CONFIG_HWCONFIG 1 512 513#endif /* __CONFIG_H */ 514